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PCA9641BSHP Datasheet(PDF) 41 Page - NXP Semiconductors

Part # PCA9641BSHP
Description  2-channel I2C-bus master arbiter
PDF  55 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCA9641BSHP Datasheet(HTML) 41 Page - NXP Semiconductors

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PCA9641
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 2.1 — 27 October 2015
41 of 55
NXP Semiconductors
PCA9641
2-channel I2C-bus master arbiter
[1]
VDD must be lowered to 0.7 V in order to reset part
[2]
Typical VDD = 3.0 V at room temperature
[3]
See Table 4
[4]
Typical VDD = 2.3 V at room temperature, nominal device
[5]
Guaranteed by characterization
[6]
When RESET = VSS, IDD and Istb increase approximately 4.5 mA
19. Dynamic characteristics
Pass gate
Ron
ON-state resistance
VO = 0.4 V; IO =20mA
VDD = 3.0 V to 3.6 V
-
7.9[2]
11.5
VDD = 2.3 V to 2.7 V
-
9.9[4]
14.5
Vo(sw)
switch output voltage
Io(sw) = 100 A
Vi(sw) =VDD = 3.6 V
1.6
2.0[2]
2.8
V
Vi(sw) =VDD =2.3 V
1.1
1.4[4]
2.2
V
IL
leakage current
VI =VDD or VSS
1-
+1
A
INT0 and INT1 outputs
IOL
LOW-level output current VOL =0.4 V
3
-
-
mA
Table 19.
Static characteristics …continued
VDD = 2.3 V to 3.6 V; VSS =0V; Tamb = 40 C to +85 C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Table 20.
Dynamic characteristics
Symbol
Parameter
Conditions
Standard-mode
I2C-bus
Fast-mode
I2C-bus
Fast-mode Plus
I2C-bus
Unit
Min
Max
Min
Max
Min
Max
tPD
propagation delay (SDA_MSTn to
SDA_SLAVE) or
(SCL_MSTn to
SCL_SLAVE)
[1]
-
0.3
-
0.3
-
0.3
ns
fSCL
SCL clock
frequency
20
100
20
400
20
1000 kHz
fSCL(init/rec)
SCL clock
frequency
(bus initialization/
bus recovery)
[8]
18
50
18
50
18
50
kHz
tBUF
bus free time
between a STOP
and START
condition
4.7
-
1.3
-
0.5
-
s
tHD;STA
hold time
(repeated)
START condition
[2]
4.0
-
0.6
-
0.26
-
s
tLOW
LOW period of
the SCL clock
4.7
-
1.3
-
0.5
-
s
tHIGH
HIGH period of
the SCL clock
4.0
-
0.6
-
0.26
-
s



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