P4C188/188L

Page 5 of 12

Document # SRAM112 REV A

12. Transition is measured ±200mV from steady state voltage prior to

change with specified loading in Figure 1. This parameter is

sampled and not 100% tested.

Notes:

9. CE and WE must be LOW for WRITE cycle.

10. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state.

11. Write Cycle Time is measured from the last valid address to the first

transition address.

TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE

WE

WE

WE

AC CHARACTERISTICS - WRITE CYCLE

(V

(2)

Sym.

Parameter

-10

-12

-15

-20

-25

-35

-45

Unit

Min

Min

Min

Min

Min

Min

Min

Max

Max

Max

Max

Max

Max

Max

t

WC

t

CW

t

AW

t

AS

t

WP

t

AH

t

DW

t

DH

t

WZ

t

DW

Write Cycle Time

Chip Enable

Time to

End of Write

Address Valid

to End of Write

Address

Set-up Time

Write Pulse

Width

Address Hold

Time from

End of Write

Data Valid to

End of Write

Data Hold

Time

Write Enable

to Output in

High Z

Output Active

from End

of Write

10

7

7

0

8

0

5

0

2

5

12

8

8

0

9

0

6

0

2

6

13

10

10

0

10

0

7

0

2

6

20

13

15

0

13

0

8

0

2

8

25

15

20

0

15

0

10

0

2

35

25

25

0

25

0

15

0

3

15

45

35

35

0

35

0

20

5

3

20

ns

ns

ns

ns

ns

ns

ns

ns

ns

ns

10