CYIS1SM0250-AA
Document Number: 38-05713 Rev. *B
Page 13 of 24
Loading the X- and Y- Start Positions
The start positions (start addresses) for "ROI" (Region Of
Interest) are preloaded in the X or Y start register. They
become effective by the application of the SYNC_X,
SYNC_YL and/or SYNC_YR. The start X- or Y address must
be
applied
to
their
common
address
bus,
and
the
corresponding LD_X or LD_Y pin must be pulsed.
On each falling edge of CLK_X, a new pixel of the same row
(line) is accessed. The output stage is in hold when CLK_X is
low and starts generating a new output after a rising edge on
CLK_X.
The following timing constraints apply:
Load the X or Y start addresses in advance, before the X or Y
shift registers are preset by a SYNC pulse. However, if
necessary, they can be load just before the SYNC_X or
SYNC_Y pulse as shown in the Figure 11.
E.g. the X start register can be loaded during the row idle time.
The Y start register can be loaded during readout of the last
row of the previous frame.
If the X or Y start address does not change for later frames, it
does not need to be reloaded in the register.
T6
0.8
µs
Delay between falling edge on RESET and falling edge on R.
T7
20 ns
0.1
µs
Delay between falling edge on S and rising edge on RESET.
T8
0
1
µs
Delay between falling edge on L/R and falling edge on CLK_Y.
T9
100 ns
1
µs
Duration of cal pulse. The CAL pulse is given once each frame.
T10
0
2
µs
Delay between falling edge of SYNC_YL and rising edge of CAL pulse.
T11
40 ns
0.1
µs
Delay between falling edge on R and rising edge on L/R.
T12
0.1
µs1 µs
Delay between rising edge of CLK_Y and falling edge on S.
T13
0.5
µs
Pulse width SYNC_YL / YR
T14
0.5
µs
Pulse width CLK_YL / YR
T15
10 ns
Address set-up time
T16
20 ns
Load X / Y start register value
T17
10 ns
Address stable after load
T18
10 ns
T19
20 ns
SYNC_X pulse width. SYNC_X while CLK_X is high.
T20
10 ns
T21
40 ns
Analogue output is stable during CLK_X low.
T22
40 ns
CLK_X pulse width: During this clock phase the analogue output ramps to the next
pixel level.
T23
125 ns
ADC digital output stable after falling edge of CLK_ADC
Table 7. Readout Timing Specifications (continued)
Symbol
Min
Typ
Description
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