LC87F5LP6A

No.A0664-15/28

Recommended Operating Range at Ta = -20°C to +70°C, VSS1 = VSS2 = VSS3 = VSS4 = 0V

Specification

Parameter

Symbol

Pins/Remarks

Conditions

VDD[V]

min

typ

max

unit

0.245

µs≤ tCYC≤200µs

4.5

5.5

0.367

µs≤ tCYC≤200µs

3.0

5.5

Operating

supply voltage

(Note2-1)

VDD(1)

VDD1=VDD2

=VDD3=VDD4

0.588

µs≤ tCYC≤200µs

2.5

5.5

Memory

sustaining

supply voltage

VHD

VDD1=VDD2

=VDD3=VDD4

RAM and register contents in

HOLD mode.

2.0

5.5

VIH(1)

Ports 1, 2, 3

SI2P0 to SI2P3

P71 to P73

P70 port input/

interrupt side

2.5 to 5.5

0.3VDD

+0.7

VDD

VIH(2)

Ports 0, 8

Ports A, B, C, E, F

PWM0, PWM1

2.5 to 5.5

0.3VDD

+0.7

VDD

VIH(3)

P70 Watchdog timer

side

2.5 to 5.5

0.9VDD

VDD

High level input

voltage

VIH(4)

XT1, XT2, CF1,

RES

2.5 to 5.5

0.75VDD

VDD

VIL(1)

Ports 1, 2, 3

SI2P0 to SI2P3

P71 to P73

P70 port input/

interrupt

2.5 to 5.5

VSS

0.1VDD

+0.4

VIL(2)

Ports 0, 8

Ports A, B, C, E, F

PWM0, PWM1

2.5 to 5.5

VSS

0.15VDD

+0.4

VIL(5)

Port 70 Watchdog

timer

2.5 to 5.5

VSS

0.8VDD

-1.0

Low level input

voltage

VIL(6)

XT1, XT2, CF1,

RES

2.5 to 5.5

VSS

0.25VDD

V

4.5 to 5.5

0.245

200

3.0 to 5.5

0.367

200

Instruction cycle

time

tCYC

(Note2-2)

2.5 to 5.5

0.588

200

µs

4.5 to 5.5

0.1

12

3.0 to 5.5

0.1

8

• CF2 pin open

• System clock frequency

division rate=1/1

• External system clock

duty=50±5%

2.5 to 5.5

0.1

5

4.5 to 5.5

0.2

24.4

3.0 to 5.5

0.2

16

External system

clock frequency

FEXCF(1)

CF1

• CF2 pin open

• System clock frequency

division rate=1/2

2.5 to 5.5

0.2

10

MHz

FmCF(1)

CF1, CF2

10MHz ceramic oscillation

See Fig. 1.

4.5 to 5.5

10

FmCF(2)

CF1, CF2

8MHz ceramic oscillation

See Fig. 1.

3.0 to 5.5

8

FmCF(3)

CF1, CF2

4MHz ceramic oscillation

See Fig. 1.

2.5 to 5.5

5

FmCF(4)

CF1, CF2

12MHz ceramic oscillation

See Fig. 1.

4.5 to 5.5

12

FmRC

Internal RC oscillation

2.5 to 5.5

0.3

1.0

2.0

FmMRC

Frequency variable RC

oscillation source oscillation

2.5 to 5.5

16

MHz

Oscillation

frequency

range

(Note2-3)

FsX’tal

XT1, XT2

32.768kHz crystal oscillation.

See Fig. 2.

2.5 to 5.5

32.768

kHz

Note 2-1: VDD must be held greater than or equal to 3.0V in the flash ROM onboard programming mode.

Note 2-2: Relationship between tCYC and oscillation frequency is 3/FmCF at a division ratio of 1/1 and 6/FmCF at

a division ratio of 1/2.

Note 2-3: See Tables 1 and 2 for the oscillation constants.