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MB91F314 Datasheet(PDF) 2 Page - fujitsu semiconductor

Part # MB91F314
Description  32-bit Microcontroller
PDF  73 Pages
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Manufacturer  FUJITSU [fujitsu semiconductor]
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Logo FUJITSU - fujitsu semiconductor

MB91F314 Datasheet(HTML) 2 Page - fujitsu semiconductor

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MB91314A Series
2
• Interrupt (PC, PS save) : 6 cycles, 16 priority levels
• Harvard architecture allowing program access and data access to be executed simultaneously
• Instruction prefetch feature added by a 4-word queue in the CPU
• Instruction set compatible with FR family
2.
Simple External Bus interface
Capable of functioning 8-bit or 16-bit multiplex bus by setting with program
• Operating frequency : Max 16.5 MHz
• 8/16-bit data/address multiplex I/O
• Capable of chip-select signal output for completely independent four areas settable in 64 Kbytes minimum
• Basic bus cycle : 2 cycles
• Programmable automatic wait cycle generator capable of inserting wait cycles for each area
3.
Internal Memory
MB91314A : 256 Kbytes Mask ROM, RAM 32 Kbytes
MB91F314 : 512 Kbytes Flash, RAM 32 Kbytes
4.
DMAC (DMA Controller)
• 5 channels
• Two forwarding factors (internal peripheral/software)
• Addressing mode 20/24-bit address selection (increment/decrement/fixed)
• Transfer modes (burst transfer/step transfer/block transfer)
• Selectable transfer data size : 8, 16, or 32 bits
5.
Bit Search Module (for REALOS)
Search for the position of the bit 1/0-changed first in one word from the MSB
6.
Reload Timer (Including 1 Channel for REALOS)
• 16-bit timer ch.6
• The internal clock is optional from 2/8/32 division
7.
Multi function Serial Interface
• 11 channels
• Full duplex double buffer
• Capable of selecting communication mode : asynchronous (Start-Stop synchronous) communication,
clock synchronous communication (8.25 Mbps Max), I2C* standard mode (100 kbps Max),
high-speed mode (400 kbps Max)
• Parity on/off selectable
• Baud rate generator per channel
• Abundant error detection functions are provided (parity, frame, and overrun)
• External clock can be used as transfer clock
• Ch.0 to ch.2 correspond to DMA transfer.
• Ch.0 to ch.2 have a pair of 16 bytes FIFO buffers for transmission and reception.
•I2C bridge feature (among channels 0, 1, and 2)
• SPI mode
(Continued)



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