405EZ datasheet(9/54 Pages) AMCC

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PPC405EZ – PowerPC 405EZ Embedded Processor

Revision 1.27 - August 22, 2007

AMCC Proprietary

Preliminary Data Sheet

DCR Bus

The daisy-chained DCR bus provides a path for passing status and control information between the processor core

and the other on-chip cores. All DCRs are 32 bits in width.

On-Chip Memory (OCM) Controller

The OCM controller connects the 405EZ processor core to two non-overlapping banks of single-port, on-chip,

configurable 32KB SRAM memory. The OCM can also transfer data between the PLB and internal SRAM banks.

Features include:

• Simultaneous PLB3, instruction-Side OCM and data-Side OCM access

• PLB slave cycles support:

– 64-bit slave attachment addressable by any PLB master

– Single-beat read and write (1 to 8 bytes)

– 4-, 8-, and 16-word line read and write

– Double word and word read and write bursts

– Slave-terminated double word and word bursts

– Master-terminated variable length bursts

– Data parity generation and checking

– Read/Write protection per bank

• Instruction side interface supports:

– One-Wait state OCM access with 1-deep write buffer

– Data parity checking

• Data side interface supports:

– One-wait state OCM access with 1-deep write buffer

– Data parity generation and checking

– Read/Write protection per bank

• Processor side data port has highest access priority (maintains predictable memory accesses to OCM)

External Bus Controller

The external bus controller (EBC) transfers data between the PLB and external memory or peripheral devices

attached to the external peripheral bus. The EBC provides direct attachment of memory devices such as ROM and

SRAM, DMA device paced memory devices, and DMA peripheral devices.

Features include:

• Up to 83 MHz speed

• 8-, 16-, or 32-bit data bus, 28-bit address bus

• Up to eight chip selects

• Arbitration and multi-master supported

• Flash ROM interface

• Boot from EBC (including NAND Flash interface) support

• Direct support for 8-,16-, or 32-bit SRAM and external peripherals

• CRAM/PSRAM support

NAND Flash Controller

The NAND Flash controller (NDFC) provides a simple interface between the External Bus Controller (EBC) and a

variety of NAND Flash-based storage devices.

Features include:

• Attachment as internal EBC slave device (refer to the PPC405EZ Embedded Processor User’s Manual for

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