PPC405GPR-3JB266Z datasheet(9/57 Pages) AMCC

9 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

On-Chip Memory (OCM)

The OCM feature comprises a memory controller and a one-port 4KB static RAM (SRAM) accessed by the

processor core.

Features include:

• Low-latency access to critical instructions and data

• Performance identical to cache hits without misses

• Contents change only under program control

PLB to PCI Interface

The PLB to PCI interface core provides a mechanism for connecting PCI devices to the local PowerPC processor

and local memory. This interface is compliant with version 2.2 of the PCI Specification.

Features include:

• Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 66MHz. Internal arbiter use is

optional and can be disabled for systems which employ an external arbiter.

• PCI bus frequency up to 66MHz

- Synchronous operation at 1/n fractions of PLB speed (n = 1 to 4) to 33MHz maximum

- Asynchronous operation from 1/8 PLB frequency to 66MHz maximum

• 32-bit PCI address/data bus

• Power Management:

- PCI Bus Power Management v1.1 compliant

• Supports 1:1, 2:1, 3:1, 4:1 clock ratios from PLB to PCI

• Buffering between PLB and PCI:

- PCI target 64-byte write post buffer

- PCI target 96-byte read prefetch buffer

- PLB slave 32-byte write post buffer

- PLB slave 64-byte read prefetch buffer

• Error tracking/status

• Supports PCI target side configuration

• Supports processor access to all PCI address spaces:

- Single-byte PCI I/O reads and writes

- PCI memory single-beat and prefetch-burst reads and single-beat writes

- Single-byte PCI configuration reads and writes (type 0 and type 1)

- PCI interrupt acknowledge

- PCI special cycle

PPC405GPR-3JB266Z Datasheet(PDF) 9 Page - Applied Micro Circuits Corporation