PPC405GPR-3JB266Z datasheet(12/57 Pages) AMCC

12 / 57 page

405GPr – Power PC 405GPr Embedded Processor

AMCC

Revision 2.04 – September 7, 2007

Data Sheet

Serial Interface

• One 8-pin UART and one 4-pin UART interface provided

• Selectable internal or external serial clock to allow a wide range of baud rates

• Register compatibility with NS16550 register set

• Complete status reporting capability

• Transmitter and receiver are each buffered with 16-byte FIFOs when in FIFO mode

• Fully programmable serial-interface characteristics

• Supports DMA using internal DMA engine

IIC Bus Interface

• Compliant with Philips® Semiconductors I2C Specification, dated 1995

• Operation at 100kHz or 400kHz

•8-bit data

• 10- or 7-bit address

• Slave transmitter and receiver

• Master transmitter and receiver

• Multiple bus masters

• Supports fixed VDD IIC interface

• Two independent 4 x 1 byte data buffers

• Fifteen memory-mapped, fully programmable configuration registers

• One programmable interrupt request signal

• Provides full management of all IIC bus protocol

• Programmable error recovery

General Purpose IO (GPIO) Controller

• Controller functions and GPIO registers are programmed and accessed via memory-mapped OPB bus master

accesses

• 23 of 24 GPIOs are pin-shared with other functions. DCRs control whether a particular pin that has GPIO

capabilities acts as a GPIO or is used for another purpose. The 23 GPIOs are multiplexed with:

- 7 of 8 chip selects

- All 13 external interrupts

- All nine instruction trace pins

• Each GPIO output is separately programmable to emulate an open-drain driver (i.e., drives to zero, three-

stated if output bit is 1)

PPC405GPR-3JB266Z Datasheet(PDF) 12 Page - Applied Micro Circuits Corporation