NT5DS16M16CS datasheet(39/76 Pages) NANOAMP

39 / 76 page

Write to Read: Minimum DQSS, Odd Number of Data (3 bit Write), Interrupting (CAS

Latency = 2; Burst Length = 8)

DI a-b = data in for bank a, column b.

An interrupted burst is shown, 3 data elements are written.

2 subsequent elements of data in are applied in the programmed order following DI a-b.

tWTR is referenced from the first positive CK edge after the last desired data in pair (not the last desired data in element)

The Read command masks the last 2 data elements in the burst.

A10 is Low with the Write command (Auto Precharge is disabled).

The Read and Write commands are not necessarily to the same bank.

Don’t Care

NOP

Read

Write

NOP

Command

Address

BAa, COL b

BAa, COL n

tWTR

DI a-b

DQS

CL = 2

tDQSS (min)

1 = This bit is correctly written into the memory array if DM is low.

2 = These bits are incorrectly written into the memory array if DM is low.

NT5DS64M4CT, NT5DS32M8CT, NT5DS16M16CT

NT5DS64M4CS, NT5DS32M8CS, NT5DS16M16CS

DOC # 14-02-044 Rev A ECN # 01-1116

The specifications of this device are subject to change without notice. For latest documentation, see http://www.nanoamp.com

NanoAmp Solutions, Inc.

NT5DS16M16CS Datasheet(PDF) 39 Page - NanoAmp Solutions, Inc.