HT46R34 datasheet(14/43 Pages) HOLTEK

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HT46R32/HT46R34

Rev. 1.10

March 16, 2007

Bit No.

Label

Function

PSC0

PSC1

PSC2

Defines the prescaler stages, PSC2, PSC1, PSC0=

000: fINT=fSYS

001: fINT=fSYS/2

010: fINT=fSYS/4

011: fINT=fSYS/8

100: fINT=fSYS/16

101: fINT=fSYS/32

110: fINT=fSYS/64

111: fINT=fSYS/128

3TE

Defines the TMR active edge of the timer/event counter:

In Event Counter Mode (TM1,TM0)=(0,1):

1:count on falling edge;

0:count on rising edge

In Pulse Width measurement mode (TM1,TM0)=(1,1):

1: start counting on the rising edge, stop on the falling edge;

0: start counting on the falling edge, stop on the rising edge

TON

Enable or disable the timer counting

(0=disable; 1=enable)

Unused bits, read as

²0²

TM0

TM1

Defines the operating mode (TM1, TM0)=

01=Event count mode (external clock)

10=Timer mode (internal clock)

11=Pulse width measurement mode

00=Unused

TMRC (0EH) Register

Timer/Event Counter

A timer/event counter is implemented in the

microcontroller. The timer/event counter contains an

8-bit programmable count-up counter whose clock

source may come from an external source or from the

system clock.

Using an external clock input allows the user to count

external events, measure time internals or pulse widths,

or generate an accurate time base. While using the in-

ternal clock allows the user to generate an accurate time

base.

The timer/event counter can generate a PFD signal by

using the external or internal clock. The PFD frequency

is determined by the equation fINT/[2

´(256-N)].

There are 2 registers related to the timer/event counter;

TMR and TMRC. Two physical registers are mapped to

the TMR location. Writing to TMR places the start value

in the timer/event counter preload register, while read-

ing TMR retrieves the contents of the timer/event coun-

ter. The TMRC register is a timer/event counter control

The TM0 and TM1 bits define the operating mode. The

event count mode is used to count external events,

which means the clock source emanates from the exter-

nal TMR pin. The timer mode functions as a normal

timer with the clock source coming from the fINT clock.

The pulse width measurement mode can be used to count

the high or low level duration of the external signal on TMR.

The counting is based on fINT.

In the event count or timer mode, once the timer/event

counter starts counting, it will count from the current

contents in the timer/event counter to FFH. Once an

overflow occurs, the counter is reloaded from the

timer/event counter preload register and generates an

interrupt request flag, TF, which is bit 5 of INTC, at the

same time.

In the pulse width measurement mode with the TON and

TE bits equal to one, once TMR has received a transient

from low to high (or high to low if the TE bits is

²0²) it will

start counting until TMR returns to the original level and

resets the TON bit. The measured result will remain in the

timer/event counter even if the activated transient occurs

again. Therefore only a one cycle measurement is made.

Not until the TON bit is once again set, will the cycle mea-

surement function again if further transient pulses are re-

ceived. Note that, in this operating mode, the timer/event

counter starts counting not according to the logic level but

according to the transient edges. In the case of counter

overflows, the counter is reloaded from the timer/event

counter preload register and issues the interrupt request

just like the other two modes. To enable the counting op-

eration, the timer ON bit,TON, which is bit 4 of TMRC,

should be set to 1. In the pulse width measurement

mode, the TON bit will be cleared automatically after the

measurement cycle is completed. But in the other two

modes the TON bit can only be reset by instructions. The

overflow of the timer/event counter is one of the wake-up

sources. No matter what the operation mode is, writing a

0 to ETI can disable the interrupt service.

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