HT46R34 datasheet(16/43 Pages) HOLTEK

16 / 43 page

HT46R32/HT46R34

Rev. 1.10

March 16, 2007

After a device reset, the input/output lines will default to

inputs and remain at a high level or floating state, de-

pendent upon the pull-high configuration options. Each

bit of these input/output latches can be set or cleared by

the

²SET [m].i² and ²CLR [m].i² (m=12H, 14H, 16H or

18H) instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of port A has the capability of waking-up the

device.

Each I/O line has a pull-high option. Once the pull-high

configuration option is selected, the I/O line has a

pull-high resistor, otherwise, there

¢s none. Take note

that a non-pull-high I/O line operating in input mode will

cause a floating state.

Pin PA3 is pin-shared with the PFD signal. If the PFD

configuration option is selected, the output signal in the

output mode for PA3 will be the PFD signal generated by

the timer/event counter overflow signal. The input mode

always retains its original functions. Once the PFD op-

tion is selected, the PFD output signal is controlled by

the PA3 data register only. Writing a

²1² to the PA3 data

²0² will force the PA3 to remain at ²0². The I/O functions

for PA3 are shown below.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PFD)

O/P

(PFD)

PA3

Logical

Input

Logical

Output

Logical

Input

PFD

(Timer on)

Note:

The PFD frequency is the timer/event counter

overflow frequency divided by 2.

Pins PA5 and PA4 are pin-shared with INT and TMR

pins respectively.

The PB can also be used as A/D converter inputs. The

A/D function will be described later. There are two PWM

functions shared with pins PD0 and PD1. If the PWM

functions are enabled, the PWM signals will appear on

PD0 and PD1, the pins are setup as outputs. Writing a

²1² to the PD0 or PD1 data register will enable the PWM

outputs to function while writing a

²0² will force the PD0

and PD1 outputs to remain at

²0². The I/O functions of

PD0 and PD1 are as shown.

I/O

Mode

I/P

(Normal)

O/P

(Normal)

I/P

(PWM)

O/P

(PWM)

PD0

PD1

Logical

Input

Logical

Output

Logical

Input

PWM0

PWM1

It is recommended that unused I/O lines should be setup

as output pins by software instructions to avoid consum-

ing power under input floating states.

PWM

The microcontroller provides a 2 channel (6+2) bits

PWM0/PWM1 output shared with PD0/PD1. The PWM

channel has its data register denoted as PWM0 and

PWM1. The frequency source of the PWM counter co-

mes from fSYS. The PWM register is an eight bit register.

Once PD0/PD1 are selected as PWM outputs and the

output function of PD0/PD1 is enabled (PDC.0=

²0² or

PDC.1=

²0²), writing a 1 to the PD0/PD1 data register

will enable the PWM output function while writing a

²0²

will force the PD0/PD1 outputs to stay at

²0².

A PWM cycle is divided into four modulation cycles

(modulation cycle 0~modulation cycle 3). Each modula-

tion cycle has 64 PWM input clock period. In a (6+2) bit

PWM function, the contents of the PWM register is di-

vided into two groups. Group 1 of the PWM register is

denoted by DC which is the value of PWM.7~PWM.2.

Group 2 is denoted by AC which is the value of

PWM.1~PWM.0.

In a PWM cycle, the duty cycle of each modulation cycle

is shown in the table.

Parameter

AC (0~3)

Duty Cycle

Modulation cycle i

(i=0~3)

i<AC

DC+1

³AC

The modulation frequency, cycle frequency and cycle

duty of the PWM output signal are summarized in the

following table.

PWM

Modulation

Frequency

PWM Cycle

Frequency

PWM Cycle

Duty

fSYS/64

fSYS/256

[PWM]/256

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