HT46R34 datasheet(17/43 Pages) HOLTEK

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HT46R32/HT46R34

Rev. 1.10

March 16, 2007

A/D Converter

A 4 channel 12-bit resolution A/D converter is imple-

mented in the microcontrollers. The reference voltage

for the A/D is VDD. The A/D converter contains 4 special

registers, which are; ADRL, ADRH, ADCR and ACSR.

The ADRH and ADRL registers are the A/D conversion

result register higher-order byte and lower-order byte

and are read-only. After the A/D conversion has com-

pleted, the ADRL and ADRH registers should be read to

get the conversion result data. The ADCR register is an

A/D converter control register, which defines the A/D

channel number, analog channel select, start A/D con-

version control bit and the end of A/D conversion flag. It

is used to start an A/D conversion, define the PB config-

uration, select the converted analog channel, and give

the START bit a raising edge and a falling edge

®1®0). At the end of an A/D conversion, the EOCB

bit is cleared and an A/D converter interrupt occurs, if

the A/D converter interrupt is enabled. The ACSR

select the A/D clock source.

The A/D converter control register is used to control the

A/D converter. Bit2~bit0 of the ADCR regsiter are used

to select an analog input channel. There are a total of

four channels to select. Bit5~bit3 of the ADCR register

are used to set the PB configurations. PB can be config-

ured as an analog input or as a digital I/O line decided by

these 3 bits. Once a PB line is selected as an analog in-

put, the I/O functions and pull-high resistor of this I/O

line are disabled, and the A/D converter circuit is

powered on. The EOCB bit, bit6 of ADCR, is the end of

A/D conversion flag. This bit is monitored to check when

the A/D conversion has completed. The START bit of

the ADCR register is used to initiate the A/D conversion

process. When the START bit is provided with a raising

edge and then a falling edge, the A/D conversion pro-

cess will begin. In order to ensure that the A/D conver-

sion is completed, the START should remain at

²0² until

the EOCB flag is cleared to

²0² which indicates the end

of the A/D conversion.

Bit 7 of the ACSR register is used for test purposes only

and must not be used for other purposes by the applica-

tion program. Bit1 and bit0 of the ACSR register are

used to select the A/D clock source.

When the A/D conversion has completed, the A/D inter-

rupt request flag will be set. The EOCB bit is set to

²1²

when the START bit is set from

²0² to ²1².

Important Note for A/D initialisation:

Special care must be taken to initialise the A/D con-

verter each time the Port B A/D channel selection bits

are modified, otherwise the EOCB flag may be in an un-

defined condition. An A/D initialisation is implemented

by setting the START bit high and then clearing it to zero

within 10 instruction cycles of the Port B channel selec-

tion bits being modified. Note that if the Port B channel

selection bits are all cleared to zero then an A/D

initialisation is not required.

ADRL

¾¾¾¾

ADRH

D11 D10 D9

Note:

D0~D11 is A/D conversion result data bit

LSB~MSB.

ADRL (20H), ADRH (21H) Register

f S Y S / 2

P W M

[ P W M ] = 1 0 0

[ P W M ] = 1 0 1

P W M

[ P W M ] = 1 0 2

P W M

[ P W M ] = 1 0 3

P W M

P W M c y c l e : 2 5 6 / f S Y S

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

2 5 / 6 4

2 6 / 6 4

M o d u l a t i o n c y c l e 0

P W M m o d u l a t i o n p e r i o d : 6 4 / f S Y S

M o d u l a t i o n c y c l e 1

M o d u l a t i o n c y c l e 2

M o d u l a t i o n c y c l e 3

M o d u l a t i o n c y c l e 0

PWM

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