HT48R062/HT48C062

Rev. 1.11

10

October 30, 2006

After a chip reset, these input/output lines remain at high

levels or floating state (dependent on pull-high options).

Each bit of these input/output latches can be set or

cleared by

²SET [m].i² and ²CLR [m].i² (m=12H or 14H)

instructions.

Some instructions first input data and then follow the

output operations. For example,

²SET [m].i², ²CLR

[m].i

², ²CPL [m]², ²CPLA [m]² read the entire port states

into the CPU, execute the defined operations

(bit-operation), and then write the results back to the

latches or the accumulator.

Each line of Port A has the capability of waking-up the

device. The highest 5-bit of Port B are not physically im-

plemented; on reading them a

²0² is returned whereas

writing then results in a no-operation. See Application

note.

There are pull-high options available for PA and PB.

Once the pull-high option is selected, I/O lines have

pull-high resistors. Otherwise, the pull-high resistors are

absent. It should be noted that a non-pull-high I/O line

operating in input mode will cause a floating state.

Low Voltage Reset

- LVR

The microcontroller provides low voltage reset circuit in

order to monitor the supply voltage of the device. If the

supply voltage of the device is within the range

tomatically reset the device internally.

The LVR includes the following specifications:

original state to exceed 1ms. If the low voltage state

does not exceed 1ms, the LVR will ignore it and do not

perform a reset function.

²OR² function with the external

RES signal to perform chip reset.

Note:

tion at 4MHz system clock.

5 . 5 V

3 . 0 V

2 . 2 V

0 . 9 V

5 . 5 V

5 . 5 V

0 . 9 V

0 V

R e s e t S i g n a l

R e s e t

* 1

* 2

N o r m a l O p e r a t i o n

R e s e t

L V R D e t e c t V o l t a g e

Low Voltage Reset

Note:

*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system

clock pulses before entering the normal operation.

*2: Since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters

the reset mode.