STVM100

Device operation

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2.1.5

Acknowledge

Each byte of eight bits is followed by one Acknowledge bit. This Acknowledge bit is a low

level signal put on the bus by the receiver, whereas the master generates an extra

acknowledge-related clock pulse (see Figure 6). A slave receiver which is addressed is

obliged to generate an acknowledge signal after the reception of each byte that has been

clocked out of the slave transmitter.

The device that acknowledges transmissions has to pull down the SDA line during the

acknowledge clock pulse in such a way, that the SDA line is a stable low during the high

period of the acknowledge-related clock pulse. The setup and hold times must be taken into

account. A master receiver must signal an end of transmitted data to the slave transmitter

by not generating an acknowledge on the last byte that has been clocked out of the slave. In

this case, the transmitter must leave the data line high to enable the master to generate the

Stop condition.

Figure 6.

Acknowledgement sequence

AI00601

DATA OUTPUT

BY RECEIVER

DATA OUTPUT

BY TRANSMITTER

SCL FROM

MASTER

START

CLOCK PULSE FOR

ACKNOWLEDGEMENT

12

89

MSB

LSB