Device operation

STVM100

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2.2

Read mode

In READ mode, after the Start condition, the master sets the slave address (see Figure 7).

Followed by the READ/WRITE Mode Control bit (R/W=1) and the Acknowledge bit, the

value in DAC register will be transmitted and the master receiver will send an Acknowledge

bit to the slave transmitter. Finally the Stop condition will terminate the READ operation. In

READ mode, the valid data is the first 7 bits and the P bit (the eight bit) is don’t care.

2.3

Write mode

In WRITE mode the master transmits to the STVM100 slave receiver. The bus protocol is

shown in Figure 7. Following the Start condition and slave address, a logic '0' (R/W = 0) is

placed on the bus to identify a WRITE operation. After the acknowledgement by the slave,

the data will be transmitted to the slave with the 7-bit which indicates the data is valid as well

as the eighth bit “P” for the register’s identification. When P = 1, the DAC register is written

to, and when P = 0, the EEPROM is written to (Programming). After receiving the data, the

slave will generate an acknowledge signal, then a Stop condition will terminate the WRITE

operation. STVM100 is pre-programmed with 80H in the EEPROM after manufacturing.

A period of tW (see Table 8) is needed for EEPROM programming. During this period, the

slave will not acknowledge any WRITE operation.

The bit P values in both READ and WRITE modes are shown in Table 3.

Figure 7.

Read/write mode sequence

2.4

10ms to ensure that the EEPROM and power-on reset circuits are synchronized, and the

correct value is read from the EEPROM.

Table 3.

Bit P read and write mode values

Operation

P-bit value

Description

READ

X

Don’t care

WRITE

1

DAC register WRITE

0

EEPROM WRITE

(programming)

AI12276_b

1

START

STOP

SDA

SCL

00

1

1

1

1

10

0

1

11

1

START

SLAVE ADDRESS

R/W

A

A

65

4

3

21

0

P

65

4

3

21

0

P

A

A

STOP

R/W