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RT3612EB Datasheet(PDF) 34 Page - Richtek Technology Corporation

Part # RT3612EB
Description  2-Phase PWM Controller with Dual Integrated Drivers for IMVP9 CPU Core Power Supply
PDF  47 Pages
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Manufacturer  RICHTEK [Richtek Technology Corporation]
Direct Link  http://www.richtek.com
Logo RICHTEK - Richtek Technology Corporation

RT3612EB Datasheet(HTML) 34 Page - Richtek Technology Corporation

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RT3612EB
34
DS3612EB-02 December 2019
www.richtek.com
©
Copyright 2019 Richtek Technology Corporation. All rights reserved.
is a registered trademark of Richtek Technology Corporation.
Through PIN-SETTING, RT3612EB provides advanced
ramp magnitude tuning. FLRAMP_PS0[1:0] and
FLRAMP_PS1 are for PS0 and PS1, respectively.
According to different application conditions, the setting
of parameters are listed in Table 12 and Table 13. The
larger magnitude indicates larger parasitic inductance
suppression. However, larger magnitude also affects loop
response speed and reduce PWM output frequency at
loading edge. For normal PCB layout, FLRAMP_PS0[1:0]
= 00 or FLRAMP_PS0[1:0] = 11 are recommended. The
final setting must be based on actual measurement.
Table 12. PIN-SETTING of Advanced Ramp
Magnitude in PS0
FLRAMP_PS0
[1:0]
Internal Advanced
Ramp Magnitude (index)
00
125
01
175
10
225
11
Disable
Table 13. PIN-SETTING of Advanced Ramp
Magnitude in PS1
FLRAMP_PS1
Internal Advanced Ramp
Magnitude (index)
0
125
1
175
ACLL Performance Enhancement
RT3612EB provides another optional function to improve
undershoot by applying a positive offset at loading edge.
Controller detects COMP signal and compared it with
steady state. While VCOMP variation exceeds a threshold,
an additional positive offset will apply to the output voltage.
The threshold can be set through PIN-SETTING and
separately for PS0 and PS1, as listed in Table 14. The
smaller index indicates the easier detection being
triggered. The positive offset is related to the compensation.
It can approximate to
. In PS0, the slew
rate of VRAMP would increase when the VCOMP intersect
the positive offset. In order to send out another on-time
earlier to improve undershoot. In PS1, besides the positive
offset, an additional 10mV is applied to the DAC and one
pulse of PWM is also forced turn on while the function is
triggered. The positive offset and the 10mV DAC offset is
released gradually with about hundred microsecond. Figure
20 and Figure 21 show undershoot suppression behavior
in PS0 and PS1. For different platform, the optimized
setting is different. The final setting must be based on
actual measurement.
Table 14. PIN-SETTING of Undershoot Suppression
UDS[2:0]
PS0 (index) PS1 (index)
000
Disable
Disable
001
Disable
175
010
200
125
011
200
150
100
200
175
101
250
125
110
250
150
111
250
175
EA2
EA1
R
60mV /
R






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