RT3612EB datasheet(17/47 Pages) RICHTEK

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RT3612EB

DS3612EB-02 December 2019

www.richtek.com

is a registered trademark of Richtek Technology Corporation.

Figure 4. Timing Chart of PIN-SETTING Mechanism

PIN-SETTING Mechanism

The RT3612EB provides multiple parameters for platform

setting and BOM optimization. These parameters can be

set through SETx and TSEN pins. The RT3612EB adopts

two-step PIN-SETTING mechanism to maximize IC pin

utilization. Figure 4 shows the timing chart of PIN-

SETTING mechanism. Figure 5 illustrates this operating

mechanism for SETx.

The voltage at VREF06 pin ramps up to 3.2V after Chip

Enable = H. First, external divider voltage is sensed as

Vdivider. ADC codes Vdivider and stores in the Divider-

μAsources the divider

and generates another voltage as Vcurrent. VIXR = (Vcurrent-

Vdivider) is coded and stored in the IXR-Register. Vdivider

and Vcurrent can be represented as follows :

Figure 5. Operating Mechanism for SETx

VREF06 =

3.2V

SETx

80µA

SETx

Divider-Register

ADC

SETx

IXR-Register

VREF06 =

3.2V

SETx

80µA

ADC

SETx

Divider-Register

SETx

IXR-Register

VREF06

3.2V

80uA Switch of SETx

PIN-SETTING

Mode

VR Initial Setting Mode

Chip Enable

(VRON=H and VCC>4.45V)

VSEN (VBOOT=1.8V)

SETx

0.6V

80uA

0uA

1.8V

3.2 x R2/(R1+R2)

0.6 x R2/(R1+R2)

80uA x (R1//R2)

SETx

Divider-

SETx

IXR-Register

Offset

Cancellation1

Mode

Offset

Cancellation2

Mode

divider

current

V3.2V

R1 R2

V3.2V 80 A

R1 R2

















Divider-Register and IXR-Register set specified functions.

For example, Divider-Register of SET1 sets ICCMAX and

TON width setting; IXR-Register of SET1 sets TON width

setting and VBOOT. All setting functions are summarized

in Table 1.

RT3612EB Datasheet(PDF) 17 Page - Richtek Technology Corporation

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