This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

15

EN25B32

Rev. C, Issue Date: 2007/06/21

Table 6. Status Register Bit Locations

Note : In OTP mode, SRP bit is served as OTP_LOCK bit,

The status and control bits of the Status Register are as follows:

BUSY bit. The BUSY bit indicates whether the memory is busy with a Write Status Register, Program or

Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no such cycle is in progress.

WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch. When

set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is reset and

no Write Status Register, Program or Erase instruction is accepted.

BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the

area to be software protected against Program and Erase instructions. These bits are written with the

Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1, BP0) bits is

set to 1, the relevant memory area (as defined in Table 3.) becomes protected against Page Program (PP)

and Sector Erase (SE) instructions. The Block Protect (BP2, BP1, BP0) bits can be written provided that

the Hardware Protected mode has not been set. The Bulk Erase (BE) instruction is executed if, and only if,

both Block Protect (BP2, BP1, BP0) bits are 0.

Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will read 0 for

these bit locations. It is recommended to mask out the reserved bit when testing the Status Register. Doing this

will ensure compatibility with future devices.