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CMOS High Voltage Logic – CD4541B

Rev 1.0

11/06/20

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

VOL = 0.4V

1.9

1.55

1.08

10V

VOL = 0.5V

5

4

2.8

Minimum Output

(Sink) Current

IOL

15V

VOL = 1.5V

12.6

10

7.2

mA

Maximum Input

Leakage Current

IIN

15V

VIN = VDD or VSS

±0.1

±0.1

±1.0

µA

5V

5

5

150

10V

10

10

300

15V

20

20

600

Maximum Quiescent

Current

5

IDD

20V

VIN = VDD or VSS

100

100

3000

µA

DC Electrical Characteristics (Voltages referenced to V

SS)

5. With AUTO RESET enable additional current drain at 25°C is:

200μA (Max) at 5V;

350μA (Max) at 10V;

500μA (Max) at 15V.

6. Not production tested in die form, characterized by chip design and tested in package.

LIMITS

PARAMETER

SYMBOL

VDD

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

5V

1.5

1.5

0.75

10V

4

4

2

Maximum Clock

Frequency

(Figure 1)

fmax

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

6

6

3

MHz

5V

10.5

10.5

21

10V

3.8

3.8

7.6

2

8,

tPLH, tPHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

2.9

2.9

5.8

µs

5V

18

18

36

10V

10

10

20

Maximum

Propagation Delay,

Cloc to Q, Q

k

(Figure 1)

2

16,

tPLH, tPHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

7.5

7.5

15

µs

5V

360

360

720

10V

180

180

360

Maximum Output

Transition Time,

Any Output (Fig 1.)

tTLH

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

130

130

260

ns

5V

200

200

400

10V

100

100

200

Maximum Output

Transition Time,

Any Output (Fig. 1)

tTHL

15V

CL = 50pF,

RL = 200kΩ

tr = tf = 20ns

80

80

160

ns

Maximum

Input Capacitance

CIN

-

TA = 25°C

VIN = 0V

7.5

7.5

7.5

pF

AC Electrical Characteristics6