Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

CS4239 Datasheet(PDF) 9 Page - Cirrus Logic

Part # CS4239
Description  CrystalClear??Portable ISA Audio System
PDF  98 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

CS4239 Datasheet(HTML) 9 Page - Cirrus Logic

Back Button CS4239 Datasheet HTML 5Page - Cirrus Logic CS4239 Datasheet HTML 6Page - Cirrus Logic CS4239 Datasheet HTML 7Page - Cirrus Logic CS4239 Datasheet HTML 8Page - Cirrus Logic CS4239 Datasheet HTML 9Page - Cirrus Logic CS4239 Datasheet HTML 10Page - Cirrus Logic CS4239 Datasheet HTML 11Page - Cirrus Logic CS4239 Datasheet HTML 12Page - Cirrus Logic CS4239 Datasheet HTML 13Page - Cirrus Logic Next Button
Zoom Inzoom in Zoom Outzoom out
 9 / 98 page
background image
TIMING PARAMETERS (Continued)
Parameter
Symbol
Min
Max
Units
Parallel Bus Timing
IOW or IOR strobe width
tSTW
90
ns
Data valid to IOW rising edge
(write cycle)
tWDSU
22
ns
IOR falling edge to data valid (read cycle)
tRDDV
60
ns
SA <> and AEN setup to IOR or IOW falling edge
tADSU
22
ns
SA <> and AEN hold from IOW or IOR rising edge
tADHD
10
ns
DACK<> inactive to IOW or IOR falling edge (DMA cycle
immediately followed by a non-DMA cycle)
(Note 8)
tSUDK1
60
ns
DACK<> active from IOW or IOR rising edge (non-DMA
cycle completion followed by DMA cycle)
(Note 8)
tSUDK2
0ns
DACK<> setup to IOR falling edge (DMA cycles)
DACK<> setup to IOW falling edge
(Note 8)
tDKSUa
tDKSUb
25
25
ns
ns
Data hold from IOW rising edge
tDHD2
15
ns
DRQ<> hold from IOW or IOR falling edge
DTM(I10) = 0
(assumes no more DMA cycles needed)
DTM(I10) = 1
tDRHD
-25
45
ns
Time between rising edge of IOW or IOR to next falling
edge of IOW or IOR
tBWDN
80
ns
Data hold from IOR rising edge
tDHD1
025
ns
DACK<> hold from IOW rising edge
DACK<> hold from IOR rising edge
tDKHDa
tDKHDb
25
25
ns
ns
RESDRV pulse width high
(Note 1)
tRESDRV
1ms
Initialization Time
(Note 1, 9)
tINIT
310
ms
EEPROM Read Time
(Note 1, 10) tEEPROM
1190
ms
XTAL, 16.9344 MHz, frequency
(Notes 1, 11)
16.92
16.95
MHz
XTALI high time
(Notes 1, 11)
24
ns
XTALI low time
(Notes 1, 11)
24
ns
Sample Frequency
(Note 1)
Fs
3.918
50
kHz
CS4610 DSP Serial Port Timing
SCLK rising to SDOUT valid
(Note 1)
tPD1
60
ns
SCLK rising to FSYNC transition
(Note 1)
tPD2
-20
20
ns
SDIN valid to SCLK falling
(Note 1)
tS1
30
ns
SDIN hold after SCLK falling
(Note 1)
tH1
30
ns
Notes:
8. AEN must be high during DMA cycles.
9. Initialization time depends on the power supply circuitry, as well as the the type of clock used.
10. EEPROM read time is dependent on amount of data in EEPROM. Minimum time relates to no
EEPROM present. Maximum time relates to EEPROM data size of 1k bytes.
11. The Sample frequency specification must not be exceeded.
CrystalClear Portable ISA Audio System
TM
CS4239
DS253PP2
9



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com