The Embedded I/O Company

TPMC632

Reconfigurable FPGA with 64 TTL I/O / 32 Diff. I/O

TPMC632-10R

TPMC632-19R without heat sink

Application Information

The TPMC632 is a standard single-width 32 bit PMC

module providing a user configurable XC6SLX45T-2 or

XC6SLX100T-2 Spartan-6 FPGA. The integrated Spartan-

6’s PCIe Endpoint Block is connected to a PCIe-to-PCI

Bridge which routed to the PMC PCI Interface.

Different variants of the TPMC632 provide ESD-protected

TTL

lines,

ESD-protected

differential

I/O

lines

and

differential Multipoint-LVDS lines. Also combination of 32

TTL and 16 differential I/O lines are supported.

All lines are individually programmable as input, output or

tri-state. The receivers are always enabled, which allows

determining the state of each I/O line at any time. This can

be used as read back function for lines configured as

outputs. Each TTL I/O line has a pull resistor. The pull

voltage level is selectable to be either +3.3V, +5V and

additionally GND. The differential I/O lines are terminated

by 120

Ω resistors and the differential Multipoint-LVDS

lines are terminated by 100

Ω resistors.

The FPGA is connected to a 128 Mbytes, 16 bit wide

DDR3 SDRAM. The SDRAM-interface uses a hardwired

internal Memory Controller Block of the Spartan-6.

The FPGA is configured by a platform flash or SPI flash.

Both configuration flashes are in-system programmable.

An in-circuit debugging option is available via a JTAG

header for read back and real-time debugging of the

FPGA design (using Xilinx “ChipScope”).

The TPMC632 provides front panel I/O via a HD68 SCSI-3

type connector and rear panel I/O via P14.

User applications for the TPMC632 with XC6SLX45T-2

FPGA can be developed using the design software ISE

WebPACK which can be downloaded free of charge from

www.xilinx.com. The larger FPGA densities require a full

licensed ISE Design Suite.

TEWS offers an FPGA Development Kit (TPMC632-FDK)

which consists of well documented basic example design.

It includes an .ucf file with all necessary pin assignments

and basic timing constraints. The example design covers

the main functionalities of the TPMC632. It implements a

DMA capable PCIe endpoint with interrupt support,

register mapping, DDR3 memory access and basic I/O. It

comes as a Xilinx ISE project with source code and as a

ready-to-download bitstream.

Please note: The basic example design requires the

Embedded Development Kit (EDK), which is part of the

Embedded or System Edition of the ISE Design Suite from

Xilinx (downloadable from www.xilinx.com, a 30 day

evaluation license is available).

Software

Support

(TDRV015-SW-xx)

for

different

operating systems is available.

TEWS TECHNOLOGIES GmbH keeps the right to change technical specification without further notice.

All trademarks mentioned are property of their respective owners.

Issue 1.0.2

2017-08-31

TEWS TECHNOLOGIES GmbH

Am Bahnhof 7

25469 Halstenbek, Germany

Phone: +49 (0) 4101 4058 0

Fax: +49 (0) 4101 4058 19

e-mail: info@tews.com

www.tews.com