ST7LITEUSX datasheet(41/108 Pages) STMICROELECTRONICS

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9 I/O PORTS

9.1 INTRODUCTION

The I/O port offers different functional modes:

– transfer of data through digital inputs and outputs

and for specific pins:

– external interrupt generation

– alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 6 pins. Each pin (except

PA3/RESET) can be programmed independently

as digital input (with or without interrupt genera-

tion) or digital output.

9.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

– Data Register (DR)

– Data Direction Register (DDR)

and one optional register:

– Option Register (OR)

Each I/O pin may be programmed using the corre-

sponding register bits in the DDR and OR regis-

ters: bit X corresponding to pin X of the port. The

same correspondence is used for the DR register.

The following description takes into account the

OR register, (for specific ports which do not pro-

vide this register refer to the I/O Port Implementa-

tion section). The generic I/O block diagram is

shown in Figure 28

9.2.1 Input Modes

The input configuration is selected by clearing the

corresponding DDR register bit.

In this case, reading the DR register returns the

digital value applied to the external I/O pin.

Different input modes can be selected by software

through the OR register.

Notes:

1. Writing the DR register modifies the latch value

but does not affect the pin status.

2. PA3 cannot be configured as input.

9.2.1.1 External interrupt function

When an I/O is configured as Input with Interrupt,

an event on this I/O can generate an external inter-

rupt request to the CPU.

Each pin can independently generate an interrupt

request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the

EICR register.

Each external interrupt vector is linked to a dedi-

cated group of I/O port pins (see pinout description

and interrupt section). If several I/O interrupt pins

on the same interrupt vector are selected simulta-

neously, they are logically combined. For this rea-

son if one of the interrupt pins is tied low, it may

mask the others.

External interrupts are hardware interrupts. Fetch-

ing the corresponding interrupt vector automatical-

ly clears the request latch. Changing the sensitivity

of a particular external interrupt clears this pending

interrupt. This can be used to clear unwanted

pending interrupts.

Spurious interrupts

When enabling/disabling an external interrupt by

setting/resetting the related OR register bit, a spu-

rious interrupt is generated if the pin level is low

and its edge sensitivity includes falling/rising edge.

This is due to the edge detector input which is

switched to '1' when the external interrupt is disa-

bled by the OR register.

To avoid this unwanted interrupt, a "safe" edge

sensitivity (rising edge for enabling and falling

edge for disabling) has to be selected before

changing the OR register bit and configuring the

appropriate sensitivity again.

Caution: In case a pin level change occurs during

these operations (asynchronous signal input), as

interrupts are generated according to the current

sensitivity, it is advised to disable all interrupts be-

fore and to reenable them after the complete pre-

vious sequence in order to avoid an external inter-

rupt occurring on the unwanted edge.

This corresponds to the following steps:

1. To enable an external interrupt:

– set the interrupt mask with the SIM instruction

(in cases where a pin level change could oc-

cur)

– select rising edge

– enable the external interrupt through the OR

– select the desired sensitivity if different from

rising edge

– reset the interrupt mask with the RIM instruc-

tion (in cases where a pin level change could

occur)

2. To disable an external interrupt:

– set the interrupt mask with the SIM instruction

SIM (in cases where a pin level change could

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