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TMS320DM6435 Datasheet(PDF) 1 Page - Texas Instruments |
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TMS320DM6435 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 252 page  www.ti.com 1 TMS320DM6435 Digital Media Processor 1.1 Features TMS320DM6435 Digital Media Processor SPRS344B – NOVEMBER 2006 – REVISED NOVEMBER 2007 [Flexible Allocation] • High-Performance Digital Media Processor – 1M-Bit (128K-Byte) L2 Unified Mapped (DM6435) RAM/Cache [Flexible Allocation] – 2.5-, 2.-, 1.67-ns Instruction Cycle Time • Supports Little Endian Mode Only – 400-, 500-, 600-MHz C64x+™ Clock Rate – Eight 32-Bit C64x+ Instructions/Cycle • Video Processing Subsystem (VPSS), VPFE – 3200, 4000, 4800 MIPS Only – Fully Software-Compatible With C64x – Front End Provides: – Commercial and Automotive (Q or S suffix) • CCD and CMOS Imager Interface Grades • BT.601/BT.656 Digital YCbCr 4:2:2 (8-/16-Bit) Interface • VelociTI.2™ Extensions to VelociTI™ • Preview Engine for Real-Time Image Advanced Very-Long-Instruction-Word (VLIW) Processing TMS320C64x+™ DSP Core • Glueless Interface to Common Video – Eight Highly Independent Functional Units Decoders With VelociTI.2 Extensions: • Histogram Module • Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit • Auto-Exposure, Auto-White Balance and Arithmetic per Clock Cycle Auto-Focus Module • Two Multipliers Support Four 16 x 16-Bit • Resize Engine Multiplies (32-Bit Results) per Clock – Resize Images From 1/4x to 4x Cycle or Eight 8 x 8-Bit Multiplies (16-Bit – Separate Horizontal/Vertical Control Results) per Clock Cycle • External Memory Interfaces (EMIFs) – Load-Store Architecture With Non-Aligned – 32-Bit DDR2 SDRAM Memory Controller Support With 256M-Byte Address Space (1.8-V I/O) – 64 32-Bit General-Purpose Registers • Supports up to 333-MHz (data rate) bus – Instruction Packing Reduces Code Size and interfaces to DDR2-400 SDRAM – All Instructions Conditional – Asynchronous 8-Bit Wide EMIF (EMIFA) – Additional C64x+™ Enhancements With up to 64M-Byte Address Reach • Protected Mode Operation • Flash Memory Interfaces • Exceptions Support for Error Detection – NOR (8-Bit-Wide Data) and Program Redirection – NAND (8-Bit-Wide Data) • Hardware Support for Modulo Loop • Enhanced Direct-Memory-Access (EDMA) Auto-Focus Module Operation Controller (64 Independent Channels) • C64x+ Instruction Set Features • Two 64-Bit General-Purpose Timers (Each – Byte-Addressable (8-/16-/32-/64-Bit Data) Configurable as Two 32-Bit Timers) – 8-Bit Overflow Protection • One 64-Bit Watch Dog Timer – Bit-Field Extract, Set, Clear • Two UARTs (One with RTS and CTS Flow – Normalization, Saturation, Bit-Counting Control) – VelociTI.2 Increased Orthogonality • Master/Slave Inter-Integrated Circuit – C64x+ Extensions (I2C Bus™) • Compact 16-bit Instructions • Multichannel Buffered Serial Port (McBSP) • Additional Instructions to Support Complex Multiplies – I2S and TDM – AC97 Audio Codec Interface • C64x+ L1/L2 Memory Architecture – SPI – 256K-Bit (32K-Byte) L1P Program RAM/Cache [Flexible Allocation] – Standard Voice Codec Interface (AIC12) – 640K-Bit (80K-Byte) L1D Data RAM/Cache – Telecom Interfaces – ST-Bus, H-100 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this document. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright © 2006–2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. |
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