TMPR3927 datasheet(4/512 Pages) TOSHIBA

4 / 512 page

Table of Contents

8.4.6

SDRAM Command Register (SDCCMD) 0xFFFE_802C ..................................................................8-12

8.4.7

SGRAM Load Mask Register (SDCSMRS1) 0xFFFE_8030 ..............................................................8-13

8.4.8

SGRAM Load Color Register (SDCSMRS2)

0xFFFE_8034 ...........................................................8-13

8.5

Operation ......................................................................................................................................................8-14

8.5.1

TX3927 Signals for Different Memory Types .....................................................................................8-14

8.5.2

SDRAM Operation ..............................................................................................................................8-15

8.5.3

DIMM Flash Memory Operation .........................................................................................................8-22

8.5.4

SMROM Operation..............................................................................................................................8-25

8.5.5

SGRAM Operation ..............................................................................................................................8-27

8.5.6

Notes on Programming ........................................................................................................................8-28

8.6

Timing Diagrams ..........................................................................................................................................8-29

8.6.1

SDRAM Single Read Operation in 32-bit Bus Mode ..........................................................................8-29

8.6.2

SDRAM Single Write Operation in 32-bit Bus Mode .........................................................................8-30

8.6.3

SDRAM Burst Read Operation in 32-bit Bus Mode............................................................................8-32

8.6.4

SDRAM Burst Write Operation in 32-bit Bus Mode ...........................................................................8-33

8.6.5

SDRAM Read in 32-bit Bus Mode (Crossing Page Boundary) ...........................................................8-34

8.6.6

SDRAM Write in 32-bit Bus Mode (Crossing Page Boundary) ..........................................................8-35

8.6.7

SDRAM Slow Burst Write Operation in 32-bit Bus Mode..................................................................8-36

8.6.8

SDRAM Single Read Operation in 16-bit Bus Mode ..........................................................................8-37

8.6.9

SDRAM Single Write Operation in 16-bit Bus Mode .........................................................................8-38

8.6.10

DIMM Flash Memory Single Read Operation in 32-bit Bus Mode.....................................................8-39

8.6.11

DIMM Flash Memory Single Write Operation in 32-bit Bus Mode ....................................................8-40

8.6.12

SMROM Single Read Operation in 32-bit Bus Mode .........................................................................8-41

8.6.13

SMROM Burst Read Operation in 32-bit Bus Mode ...........................................................................8-42

8.6.14

Low Power and Power-down Mode.....................................................................................................8-43

8.6.15

SGRAM in 32-bit Bus Mode ...............................................................................................................8-46

8.6.16

External DMA Operation (Big Endian) ...............................................................................................8-49

8.6.17

External DMA Operation (Little Endian) ............................................................................................8-51

8.7

Examples of Using SDRAM ........................................................................................................................8-53

9. External Bus Controller...........................................................................................................................................9-1

9.1

Features...........................................................................................................................................................9-1

9.2

Block Diagram................................................................................................................................................9-2

9.3

Registers .........................................................................................................................................................9-3

9.3.1

Register Map ..........................................................................................................................................9-3

9.3.2

ROM Channel Control Registers (RCCR0-RCCR7) 0xFFFE_9000 (ch.0) 0xFFFE_9004 (ch.1)

0xFFFE_9008 (ch.2) 0xFFFE_900C (ch.3) 0xFFFE_9010 (ch.4) 0xFFFE_9014 (ch.5)

0xFFFE_9018 (ch.6) 0xFFFE_901C (ch.7) ..........................................................................................9-4

9.4

Operation ........................................................................................................................................................9-6

9.4.1

Bootup Options ......................................................................................................................................9-6

9.4.2

Global Options .......................................................................................................................................9-7

9.4.3

ROM Channel Control Registers ...........................................................................................................9-7

9.4.4

Clock Options ........................................................................................................................................9-7

9.4.5

Base Address and Channel Size .............................................................................................................9-8

9.4.6

Operating Modes....................................................................................................................................9-8

9.4.7

16-Bit Data Bus Operation...................................................................................................................9-10

9.4.8

SHWT Option ......................................................................................................................................9-10

9.4.9

ACK*/READY Signal Timing.............................................................................................................9-11

9.4.10

READY Input Timing..........................................................................................................................9-12

9.4.11

Addressing ...........................................................................................................................................9-13

9.4.12

ACE* Operation...................................................................................................................................9-13

9.5

Timing Diagrams ..........................................................................................................................................9-14

9.5.1

ACE* Signal Operation .......................................................................................................................9-15

9.5.2

Normal Mode 32-bit Write Operation..................................................................................................9-16

9.5.3

Normal Mode 32-bit Operation............................................................................................................9-17

9.5.4

Normal Mode 16-bit Bus Operation ....................................................................................................9-20

9.5.5

Normal Mode 16-bit Burst Operation ..................................................................................................9-24

9.5.6

Page Mode 32-bit Burst Operation ......................................................................................................9-26

9.5.7

External ACK* Mode 32-bit Operation ...............................................................................................9-28

TMPR3927 Datasheet(PDF) 4 Page - Toshiba Semiconductor

TMPR3927 Datasheet(HTML) 4 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL