TMPR3927 datasheet(83/512 Pages) TOSHIBA

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Chapter 7 Bus Operation

7-3

7.2

Bus Operation

The TX3927 performs bus operation for the following four device controllers. Before attempting to access

a particular external device, you must set the corresponding controller with the device's address space and

the number of desired wait states. For details of bus operation, refer to the relevant chapters.

External Device

Controller

Detailed Description

SDRAM, SGRAM,

SMROM, DIMM flash

memory

SDRAMC

Chapter 8

ROM, SRAM, flash

memory

ROMC

Chapter 9

Memory, I/O

DMAC

Chapter 10

PCI devices

PCIC

Chapter 12

The SDRAMC and ROMC operate in the same way regardless of whether the bus master is the TX39/H2,

DMA controller (DMAC), or PCI controller (PCIC). The DMAC does not directly access external memory

or I/O devices, but access them via the SDRAMC or ROMC. When the TX39/H2 or DMAC accesses any

device on the PCI, the PCIC acts as the memory controller for the PCI bus. When an external PCI device

accesses memory or other devices attached to the TX3927, the PCIC acts as the bus master and accesses the

TX3927’s local memory via the SDRAMC or ROMC. If the data cache is used in write back mode, however,

the TX39/H2 core does not support the snoop function, so the snoop function must be disabled for the PCIC

and DMAC.

Bus Master

Memory Controller

External Device

SDRAMC, ROMC

Local memory, I/O

TX39/H2

PCIC (initiator)

PCI device

SDRAMC, ROMC

Local memory, I/O

DMAC

PCIC (initiator)

PCI device

PCIC (target)

(external PCI device)

SDRAMC, ROMC

Local memory, I/O

Set the address space for each memory controller to ensure that the SDRAMC, ROMC, and PCIC acting

as memory controllers will not simultaneously access the same address space.

The program must ensure that the TX3927 will only initiate bus operation for accesses to the address areas

which have been properly set up in the controllers listed above (or to TX3927 internal registers). Set the

address area for the device you wish to access in the appropriate controller.

The TX3927 offers two bus speed modes: full speed bus mode and half speed bus mode. In full speed bus

mode, the external bus operates at the same frequency as the G-Bus (1/2 the CPU frequency). In half speed

bus mode, the external bus operates at 1/2 the G-Bus frequency (1/4 the CPU frequency). Boot signal

CHANHS* (ADDR[15] pin) selects the speed of SYSCLK output. Full speed mode is selected if CHANHS*

is high at the rising edge of RESET*. Half speed mode is selected if CHANHS* is low at the rising edge of

RESET*. The ROMC also contains a register used to select either mode for each channel.

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