TMPR3927 datasheet(5/512 Pages) TOSHIBA

5 / 512 page

Table of Contents

iii

9.5.8

External ACK* Mode 16-bit Operation ...............................................................................................9-32

9.5.9

READY Mode 32-bit Operation ..........................................................................................................9-34

9.6

Examples of Using Flash ROM and SRAM .................................................................................................9-36

10. DMA Controller ....................................................................................................................................................10-1

10.1

Features.........................................................................................................................................................10-1

10.2

Block Diagram..............................................................................................................................................10-2

10.3

Registers .......................................................................................................................................................10-3

10.3.1

Register Map ........................................................................................................................................10-3

10.3.2

Master Control Register (MCR) 0xFFFE_B0A4 .................................................................................10-4

10.3.3

Channel Control Registers (CCRn) 0xFFFE_B018 (ch. 0), 0xFFFE_B038 (ch. 1),

0xFFFE_B058 (ch. 2), 0xFFFE_B078 (ch. 3), ...................................................................................10-6

10.3.4

Channel Status Registers (CSRn) 0xFFFE_B01C (ch. 0), 0xFFFE_B03C (ch. 1),

0xFFFE_B05C (ch. 2), 0xFFFE_B07C (ch. 3) ...................................................................................10-9

10.3.5

Source Address Registers (SARn) 0xFFFE_B004 (ch. 0), 0xFFFE_B024 (ch. 1),

0xFFFE_B044 (ch. 2), 0xFFFE_B064 (ch. 3) ..................................................................................10-11

10.3.6

Destination Address Registers (DARn) 0xFFFE_B008 (ch. 0), 0xFFFE_B028 (ch. 1),

0xFFFE_B048 (ch. 2), 0xFFFE_B068 (ch. 3) ..................................................................................10-12

10.3.7

Chained Address Registers (CHARn) 0xFFFE_B000 (ch. 0), 0xFFFE_B020 (ch. 1),

0xFFFE_B040 (ch. 2), 0xFFFE_B060 (ch. 3) ..................................................................................10-13

10.3.8

Source Address Increment Registers (SAIn) 0xFFFE_B010 (ch. 0), 0xFFFE_B030 (ch. 1),

0xFFFE_B050 (ch. 2), 0xFFFE_B070 (ch. 3) ..................................................................................10-14

10.3.9

Destination Address Increment Registers (DAIn) 0xFFFE_B014 (ch. 0), 0xFFFE_B034 (ch. 1),

0xFFFE_B054 (ch. 2), 0xFFFE_B074 (ch. 3) ..................................................................................10-15

10.3.10 Count Registers (CNTRn) 0xFFFE_B00C (ch. 0), 0xFFFE_B02C (ch. 1),

0xFFFE_B04C (ch. 2), 0xFFFE_B06C (ch. 3) .................................................................................10-16

10.4

Operation ....................................................................................................................................................10-17

10.4.1

Dual-Address Transfers......................................................................................................................10-17

10.4.2

Chaining Operations ..........................................................................................................................10-19

10.4.3

Single-Address Transfers ...................................................................................................................10-20

10.4.4

DMA Channel Termination by the External DMADONE* Input......................................................10-20

10.4.5

Restrictions on Non-standard Increment Values ................................................................................10-21

10.4.6

Restrictions on Dual-Address Burst Transfers ...................................................................................10-22

10.4.7

DMA Transfers with On-Chip I/O Peripherals ..................................................................................10-22

10.4.8

Timing for an External DMA Request (DMAREQ) ..........................................................................10-23

10.4.9

Configuration Errors ..........................................................................................................................10-23

10.4.10 Notes on Using the DMAC FIFO ......................................................................................................10-24

10.5

Timing Diagrams ........................................................................................................................................10-26

10.5.1

Single-Address Mode, 32-bit Read Operation (ROM) ......................................................................10-26

10.5.2

Single-Address Mode, 32-bit Write Operation (SRAM)....................................................................10-28

10.5.3

Single-Address Mode, 32-bit Burst-Read Operation (ROM).............................................................10-29

10.5.4

Single-Address Mode, 32-bit Burst-Write Operation (SRAM)..........................................................10-30

10.5.5

Single-Address Mode, 16-bit Read Operation (ROM) ......................................................................10-32

10.5.6

Single-Address Mode, 16-bit Write Operation (SRAM)....................................................................10-33

10.5.7

Single-Address, Half-speed Mode, 32-bit Read Operation (ROM) ...................................................10-34

10.5.8

Single-Address, Half-speed Mode, 32-bit Write Operation (SRAM) ................................................10-35

10.5.9

Single-Address Mode, 32-bit Read Operation (SDRAM) .................................................................10-36

10.5.10 Single-Address Mode, 32-bit Write Operation (SDRAM).................................................................10-37

10.5.11 Single-Address Mode, 16-bit Burst-Read Operation (SDRAM)........................................................10-38

10.5.12 Single-Address Mode, 32-bit Burst-Read Operation (SDRAM)........................................................10-39

10.5.13 Single-Address Mode, 32-bit Burst-Write Operation (SDRAM).......................................................10-40

10.5.14 Single-Address Mode, 32-bit Last Single-Read Operation (SDRAM) ..............................................10-41

10.5.15 Single-Address Mode, 16-bit Read Operation (SDRAM) .................................................................10-42

10.5.16 Single-Address Mode, 16-bit Write Operation (SDRAM).................................................................10-43

10.5.17 Single-Address Mode, 32-bit Read Operation (SDRAM) .................................................................10-44

10.5.18 Single-Address Mode, 32-bit Write Operation (SDRAM).................................................................10-45

10.5.19 Single-Address Mode, 32-bit Burst-Write Operation (SDRAM).......................................................10-46

10.5.20 Dual-Address Mode Burst Operation (SRAM to SRAM) .................................................................10-47

10.5.21 Dual-Address Mode Burst Operation (SRAM to SDRAM)...............................................................10-48

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