TMP93CS44 datasheet(188/224 Pages) TOSHIBA

188 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-186

Watchdog Timer Mode Control Register

Bit symbol

WDTE

WDTP1

WDTP0

WARM

HALTM1

HALTM0

RESCR

DRVE

WDMOD

(005CH)

Read/Write

R/W

After reset

Function

WDT

control

0: Disable

1: Enable

Select detecting time

00: 2

15/fSYS

01: 2

17/fSYS

10: 2

19/fSYS

11: 2

21/fSYS

(See Table 3.12.1)

Warm-up

time

Standby mode

00: RUN mode

01: STOP mode

10: IDLE1 mode

11: IDEL2 mode care

1: Internally

connects

WDT out

to the

reset pin

1: Drive the

pin even

in STOP

mode

Note: When the watchdog timer is in operation, T45CR<QCU> is set to 0.

Figure 3.12.4 Watchdog Timer Related Register (1/2)

Watchdog timer out control

Don’t care

Connects WDT out to a reset

Watchdog timer enable/disable control

Disable

Enable

Please refer to the section 3.3

“Dual Clock, Standby Function”.

Selection of warm-up time when changing clock

at fc

= 20M Hz, fs = 32.768 kHz

WDMOD<WARM>

Changing to Normal (fc)

Changing to Slow (fc)

0 (2

14/oscillation frequency)

0.8192 ms

500 ms

0 (2

16/oscillation frequency)

3.2768 ms

2000 ms

Selection of warm-up time when returning from the stop mode at fc

= 20M Hz, fs = 32.768 kHz

Warm-up Time

T45CR<QCU>

= 0

T45CR<QCU>

= 1

System Clock

Selection <SYSCK>

Gear Value

<GEAR2:0>

<WARM>

= 0<WARM> = 1

<WARM>

= X

1 (fs)

XXX

(Don’t care)

0.500 s

2.000 s

3.9 ms

000 (fc)

0.8192 ms

3.277 ms

6.4

µs

001 (fc/2)

1.638 ms

6.544 ms

12.8

µs

010 (fc/4)

3.277 ms

13.107 ms

25.6

µs

011 (fc/8)

6.554 ms

26.214 ms

51.2

µs

0 (fc)

100 (fc/16)

13.107 ms

52.429 ms

102.4

µs

TMP93CS44 Datasheet(PDF) 188 Page - Toshiba Semiconductor

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