TMP93CS44 datasheet(187/224 Pages) TOSHIBA

187 / 224 page

TMP93CS44/S45

2004-02-10

93CS44-185

3.12.2

Control Registers

Watchdog timer (WDT) is controlled by two control registers WDMOD and WDCR.

(1) Watchdog timer mode register (WDMOD)

1. Setting the detecting time of watchdog timer <WDTP>

This 2-bit register is used to set the watchdog timer interrupt time for detecting

the runaway. This register is initialized to WDMOD<WDTP1:0>

= 00 when reset.

The defecting time of WDT is shown Table 3.12.1.

2. Watchdog timer enable/disable control register <WDTE>

When reset, WDMOD<WDTE> is initialized to 1 enable the watchdog timer.

To disable, it is necessary to set this bit to 0 and write the disable code (B1H) in

the watchdog timer control register WDCR. This makes it difficult for the

watchdog timer to be disabled by runaway.

However, it is possible to return from the disable state to enable state by merely

setting <WDTE> to 1.

3. Watchdog timer out reset connection <RESCR>

This register is used to connect the output of the watchdog timer with RESET

terminal, internally. Since WDMOD<RESCR> is initialized to 0 at reset, a reset

by the watchdog timer will not be performed.

(2) Watchdog timer control register (WDCR)

This register is used to disable and clear of binary counter the watchdog timer

function.

•

Disable control

By writting the disable code (B1H) in this WDCR register after clearing

WDMOD<WDTE> to 0, the watchdog timer can be disabled.

WDMOD

← 0 − − − − − X X

Clear WDMOD<WDTE> to “0”.

WDCR

← 1 0 1 1 0 0 0 1

Write the disable code (B1H).

X: Don’t care,

−: No change

•

Enable control

Set WDMOD<WDTE> to 1.

•

Watchdog timer clear control

The binary counter can be cleared and resume counting by writing clear code

(4EH) into the WDCR register.

WDCR

← 0 1 0 0 1 1 1 0

Write the clear code (4EH).

TMP93CS44 Datasheet(PDF) 187 Page - Toshiba Semiconductor

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