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TMP93CS44 Datasheet(PDF) 189 Page - Toshiba Semiconductor |
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TMP93CS44 Datasheet(HTML) 189 Page - Toshiba Semiconductor |
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189 / 224 page ![]() TMP93CS44/S45 2004-02-10 93CS44-187 Watchdog Timer Control Register 7 6 5 4 3 2 1 0 Bit symbol − WDCR (005DH) Read/Write W After reset − Function B1H: WDT disable code 4EH: WDT clear code Note: When the watchdog timer is in operation, T45CR<QCU> is set to 0. Figure 3.12.5 Watchdog Timer Related Register (2/2) Table 3.12.1 Watchdog Timer Detecting Time at fc = 20M Hz, fs = 32.768 kHz Watchdog Timer Detecting Time WDMOD<WDTP1:0> System Clock Selection <SYSCK> Gear Value <GEAR2:0> 00 01 10 11 1 (fs) XXX (Don’t care) 2.000 s 8.000 s 32.000 s 128.000 s 000 (fc) 3.277 ms 13.107 ms 52.429 ms 209.715 ms 001 (fc/2) 6.554 ms 26.214 ms 104.858 ms 419.430 ms 010 (fc/4) 13.107 ms 53.429 ms 209.715 ms 838.861 ms 011 (fc/8) 26.214 ms 104.858 ms 419.430 ms 1.678 s 0 (fc) 100 (fc/16) 52.429 ms 209.715 ms 838.861 ms 3.355 s Disable/clear WDT B1H Disable code 4EH Clear code Others Don’t care |
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