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DSP56321 Datasheet(PDF) 25 Page - Freescale Semiconductor, Inc |
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DSP56321 Datasheet(HTML) 25 Page - Freescale Semiconductor, Inc |
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25 / 84 page  AC Electrical Characteristics DSP56321 Technical Data, Rev. 11 Freescale Semiconductor 2-5 Note: If an externally-supplied square wave voltage source is used, disable the internal oscillator circuit after boot-up by setting XTLD (PCTL Register bit 2 = 1—see the DSP56321 Reference Manual). The external square wave source connects to EXTAL and XTAL is not used. Figure 2-2 shows the EXTAL input signal. 2.4.3 Clock Generator (CLKGEN) and Digital PLL (DPLL) Characteristics 4 EXTAL cycle time3 • With DPLL disabled • With DPLL enabled ETC 5.0 ns 5.0 ns ∞ 62.5 ns 4.55 ns 4.55 ns ∞ 62.5 ns 4.17 ns 4.17 ns ∞ 62.5 ns 3.64 ns 3.64 ns ∞ 62.5 ns 7 Instruction cycle time = ICYC = ETC • With DPLL disabled • With DPLL enabled ICYC 10 ns 5.0 ns ∞ 1.6 µs 9.09 ns 4.55 ns ∞ 1.6 µs 8.33 ns 4.17 ns ∞ 1.6 µs 7.28 ns 3.64 ns ∞ 1.6 µs Notes: 1. The rise and fall time of this external clock should be 2 ns maximum. 2. Refer to Table 2-6 for a description of PDF and PDFR. 3. Measured at 50 percent of the input transition. 4. The indicated duty cycle is for the specified maximum frequency for which a part is rated. The minimum clock high or low time required for correction operation, however, remains the same at lower operating frequencies; therefore, when a lower clock frequency is used, the signal symmetry may vary from the specified duty cycle as long as the minimum high time and low time requirements are met. Figure 2-2. External Input Clock Timing Table 2-6. CLKGEN and DPLL Characteristics Characteristics Symbol 200 MHz 220 MHz 240 MHz 275 MHz Unit Min Max Min Max Min Max Min Max Predivision factor PDF1 116 1 16116 1 16 — Predivider output clock frequency range PDFR 16 32 16 32 16 32 16 32 MHz Total multiplication factor 2 MF 515 5 15515 5 15 — Multiplication factor integer part MFI1 515 5 15515 5 15 — Multiplication factor numerator3 MFN 0 1270127 01270127 — Multiplication factor denominator MFD 1 128 1 128 1 128 1 128 — Double clock frequency range DDFR 160 400 160 440 160 480 160 550 MHz Phase lock-in time4 DPLT 6.85 1506 6.85 1506 6.85 1506 6.85 1506 µs Table 2-5. External Clock Operation (Continued) No. Characteristics Symbol 200 MHz 220 MHz 240 MHz 275 MHz Min Max Min Max Min Max Min Max EXTAL VILX VIHX Midpoint Note: The midpoint is 0.5 (VIHX + VILX). ETH ETL ETC 3 4 2 |
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