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ADL8113ACCZ-R7 Datasheet(PDF) 34 Page - Analog Devices

Part # ADL8113ACCZ-R7
Description  10MHz to 12GHz Low Noise Amplifier with 10MHz to 14GHz Bypass Switches
PDF  37 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADL8113ACCZ-R7 Datasheet(HTML) 34 Page - Analog Devices

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Data Sheet
ADL8113
THEORY OF OPERATION
analog.com
Rev. 0 | 34 of 37
The ADL8113 integrates an amplifier with two switching networks
located at the RF input and output. The amplifier, which is internally
AC-coupled on its input and output, uses a gallium arsenide (GaAs)
LNA die. The switching network employs robust silicon-on-insulator
(SOI) technology for fast switching and a short settling time. This
integrated solution has four different signal path modes available:
internal amplifier, internal bypass, External Bypass A, and External
Bypass B. Signal path modes are controlled through the VA and
VB digital pins. The internal amplifier is biased up by applying
5V to VDD1 and by connecting a bias resistor between VDD1
and RBIAS. The reflective switch network is powered by applying
+3.3V and −3.3V to VDD2 and VSS2, respectively. DC bias to the
switches is independent of the LNA. Turning off the bias to VDD1
that controls the LNA provides better isolation between RF ports.
SIGNAL PATH MODES FOR DIGITAL CONTROL
INPUTS
Figure 116 through Figure 119 show the signal path modes for the
digital control inputs, while Table 12 details these modes for the
digital control inputs.
Figure 116. Internal Amplifier Mode, VA = 0V and VB = 0V
Figure 117. Internal Bypass Mode, VA = 3.3V and VB = 3.3V
Figure 118. External Bypass A Mode, VA = 0V and VB = 3.3V
Figure 119. External Bypass B Mode, VA = 3.3V and VB = 0V
Table 12. Truth Table for the Signal Path Modes for the Digital Control Inputs
Mode Name
Digital Control
Signal Path Mode
VA
VB
Internal Amplifier
Low
Low
RFIN to RFOUT through the amplifier path
Internal Bypass
High
High
RFIN to RFOUT through the bypass path
External Bypass A
Low
High
RFIN to OUT_A and IN_A to RFOUT
External Bypass B
High
Low
RFIN to OUT_B and IN_B to RFOUT



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