TMP88CS42FG datasheet(102/216 Pages) TOSHIBA

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Page 92

9. 16-Bit Timer (CTC)

9.2 Control

TMP88CS42FG

Detail operation at start that varies depending on how CTC1CR2<CTC1FF0> and CTC1CR1<PPGFF0> are

set during PPG output.

By changing the port-shared output for PPG output before the counter starts counting after setting

CTC1CR2<CTC1FF0>, it is possible to determine the initial value of PPG output.

Table 9-4 Varying PPG Output Timing Depending on Settings

CTC1FF0 = 0

PPGFF0 = 0

CTC1FF0 = 1

PPGFF0 = 0

CTC1FF0 = 0

PPGFF0 = 1

CTC1FF0 = 1

PPGFF0 = 1

n+1

n+3

n+2

Internal clock

Counter

PPG output

CTC1FF0 setting

(write to CTC1CR1 Register)

Command start

or trigger start

n + 1

n + 3

n + 2

Internal clock

Counter

PPG output

CTC1FF0 setting

(write to CTC1CR1 Register)

Command start

or trigger start

n + 1

n + 3

n + 2

Internal clock

Counter

PPG output

CTC1FF0 setting

(write to CTC1CR1 Register)

Command start

or trigger start

n + 1

n + 3

n + 2

Internal clock

Counter

PPG output

CTC1FF0 setting

(write to CTC1CR1 Register)

Command start

or trigger start

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