TMP88CS42FG datasheet(98/216 Pages) TOSHIBA

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Page 88

9. 16-Bit Timer (CTC)

9.2 Control

TMP88CS42FG

9.3.4 Programmable Pulse Generate (PPG) output mode

The timer/counter starts counting as a command or edge on CTC pin input (rising/falling edge and one/both

edges respectively selected with the CTC1CR1<CTC1SE> and CTC1CR1<CTC1E>). The source clock is an

internal clock. When matched with the CTC1DR A/B/C Registers, the timer output F/F corresponding to each

mode is inverted. When matched with the CTC1DR A/B/C Registers next time, the timer output F/F is inverted

again. An INTCTC1 interrupt request is generated when the counter value matches the maximum register

value set by CTC1CR2<CTCREG>. The timer output F/F is cleared to 0 when reset. Because

CTC1CR2<CTC1FF0> can be used to set the initial value for the timer output F/F, an active-high or active-low

pulse whichever is desired can be output. The CTC1DRB and CTC1DRC Registers cannot be accessed for

write unless they are set for PPG output mode and the registers used are selected with CTC1CR2<CTC1REG>.

The number of registers set can be altered during operation. In this case, however, be sure to set the number of

registers used and write values to the data registers before the next CTC1INIT1 is output after the first

CTC1INIT1 output. Even when only altering the data register values while leaving the number of registers

unchanged, be sure to do this within the same period of time.

Figure 9-6 PPG Output Mode Timing Chart

Table 9-2 External Clock Source for Compare Timer/Counter 1

NORMAL and IDLE Modes

Maximum applied frequency [Hz]

Up to fc/22

Minimum pulse width

22/fc and over

Table 9-3 Internal Clock Source for Compare Timer/Counter 1 (Example: fc = 20 MHz)

CTC1CK

NORMAL and IDLE Modes

DV1CK = 0

DV1CK = 1

Resolution [

µs]

Maximum Setting Time [s]

Resolution [

µs]

Maximum Setting Time [s]

000

102.4

6.71

204.8

13.42

001

6.4

0.419

12.8

0.839

010

1.6

0.105

3.2

0.210

011

0.4

26.21 m

0.8

52.43 m

100

0.2

13.11 m

0.4

26.21 m

101

0.1

6.55 m

0.2

13.11 m

110

(I) One register used

When command start, interrupt output, and counter clear are set in Timer Register A

CTC pin input

Counter

Timer Register A

INTCTC1

interrupt

Command start

PPG2 pin output

Successive

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