TMP88CS43FG datasheet(23/218 Pages) TOSHIBA

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Page 13

TMP88CS43FG

Note 1: fc: the high-frequency clock [Hz], *: Don’t care

Note 2: The CGCR Register bits 4 and 3 show an indeterminate value when read.

Note 3: Be sure to write “0” to CGCR Register bits 7, 6, 2, 1 and 0.

Note 1: *: Don’t care

Note 2: Be sure to write “0” to TBTCR Register bit 4.

(2) Machine cycle

Instruction execution and the internal hardware operations are synchronized to the system clocks.

The minimum unit of instruction execution is referred to as the “mgmachine cycle”. The TLCS-

870/X series has 15 types of instructions, from 1-cycle instructions which are executed in one

machine cycle up to 15-cycle instructions that require a maximum of 15 machine cycles.

A machine cycle consists of four states (S0 to S3), with each state comprised of one main system

clock cycle.

Figure 2-5 Machine Cycles

Divider Control Register

CGCR

(0030H)

543

DV1CK

(Initial value: 000* *000)

DV1CK

Selects input clock to the first

divider stage

0: fc/4

1: fc/8

R/W

Timing Generator Control Register

TBTCR

(0036H)

543

DVOEN

DVOCK

TBTEN

TBTCK

(Initial value: 0000 0000)

Main system clock

States

1/fc

(0.20

µs at 20 MHz)

Machine cycle

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