TMP86CS25ADFG datasheet(52/194 Pages) TOSHIBA

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Page 42

3. Interrupt Control Circuit

3.4 Interrupt Sequence

TMP86CS25ADFG

Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing

3.4.3 Interrupt return

Interrupt return instructions [RETI]/[RETN] perform as follows.

As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to

restarting address, during interrupt service program.

Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and

INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and

PCH are located on address (SP + 1) and (SP + 2) respectively.

Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next inter-

rupt can be accepted immediately after the interrupt return instruction is executed.

[RETI]/[RETN] Interrupt Return

1. Program counter (PC) and program status word

(PSW, includes IMF) are restored from the stack.

2. Stack pointer (SP) is incremented by 3.

Example 1 :Returning from address trap interrupt (INTATRAP) service program

PINTxx:

POP

; Recover SP by 2

WA, Return Address

;

PUSH

; Alter stacked data

(interrupt processing)

RETN

; RETURN

Example 2 :Restarting without returning interrupt

(In this case, PSW (Includes IMF) before interrupt acceptance is discarded.)

PINTxx:

INC

; Recover SP by 3

INC

;

INC

;

(interrupt processing)

EIRL, data

; Set IMF to “1” or clear it to “0”

Restart Address

; Jump into restarting address

Interrupt

acceptance

Interrupt

service task

Restoring

registers

Saving

registers

Interrupt return

Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction

Main task

TMP86CS25ADFG Datasheet(PDF) 52 Page - Toshiba Semiconductor

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