TMP86CS64AFG datasheet(57/202 Pages) TOSHIBA

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Page 47

TMP86CS64AFG

Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return inter-

rupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example

2).

Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service

task is performed but not the main task.

3.5 Software Interrupt (INTSW)

Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW

is highest prioritized interrupt).

Use the SWI instruction only for detection of the address error or for debugging.

3.5.1 Address error detection

FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent

memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is gener-

ated and an address error is detected. The address error detection range can be further expanded by writing

FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is

fetched from RAM, DBR or SFR areas.

3.5.2 Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software break point setting

address.

3.6 Undefined Instruction Interrupt (INTUNDEF)

Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is gen-

erated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable inter-

rupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is

requested.

Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt

(SWI) does.

3.7 Address Trap Interrupt (INTATRAP)

Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address

trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary pro-

cess is broken and INTATRAP interrupt process starts, soon after it is requested.

Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on

watchdog timer control register (WDTCR).

3.8 External Interrupts

The TMP86CS64AFG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits

(Pulse inputs of less than a certain time are eliminated as noise).

Edge selection is also possible with INT1 to INT4. The INT0/P10 pin can be configured as either an external inter-

rupt input pin or an input/output port, and is configured as an input port during reset.

Edge selection, noise reject control and INT0/P10 pin function selection are performed by the external interrupt

control register (EINTCR).

TMP86CS64AFG Datasheet(PDF) 57 Page - Toshiba Semiconductor