TMP86CS64AFG datasheet(120/202 Pages) TOSHIBA

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Page 110

10. 8-Bit TimerCounter 3 (TC3)

10.1 Configuration

TMP86CS64AFG

10.3.3 Capture Mode

In the capture mode, the pulse width, frequency and duty cycle of the pulse input to the TC3 pin are mea-

sured with the internal clock. The capture mode is used to decode remote control signals, and identify AC50/60

Hz.

When the falling edge of the TC3 input is detected after the timer starts, the up-counter value is captured into

TC3DRB. Hereafter, whenever the rising edge is detected, the up-counter value is captured into TC3DRA and

the INTTC3 interrupt request is generated. The up-counter is cleared at this time. Generally, read TC3DRB and

TC3DRA during INTTC3 interrupt processing. After the up-counter is cleared, counting is continued and the

next up-counter value is captured into TC3DRB.

When the rising edge is detected immediately after the timer starts, the up-counter value is captured into

TC3DRA only, but not into TC3DRB. The INTTC3 interrupt request is generated. When the read instruction is

executed to TC3DRB at this time, the value at the completion of the last capture (FF immediately after a reset)

is read.

The minimum input pulse width must be larger than one cycle width of the source clock programmed in

TC3CR<TC3CK>.

The INTTC3 interrupt request is generated if the up-counter overflow (FFH) occurs during capture operation

before the edge is detected. TC3DRA is set to FFH and the up-counter is cleared. Counting is continued by the

up-counter, but capture operation and overflow detection are stopped until TC3DRA is read. Generally, read

TC3DRB first because capture operation and overflow detection resume by reading TC3DRA.

Figure 10-5 Capture Mode Timing Chart

Read of TC3DRA

Source

clock

Counter

TC3DRA

TC3 pin input

TC3DRB

INTTC3

interrupt request

k-1

Capture

FF (Overflow)

TC3CR<TC3S>

i+1

i-1

m+1

m-1

n-1

Internal waveform

Overflow

Timer start

TMP86CS64AFG Datasheet(PDF) 120 Page - Toshiba Semiconductor

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