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TMP86CS64AFG Datasheet(PDF) 182 Page - Toshiba Semiconductor |
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TMP86CS64AFG Datasheet(HTML) 182 Page - Toshiba Semiconductor |
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182 / 202 page  Page 172 17. 10-bit AD Converter (ADC) 17.2 Register configuration TMP86CS64AFG Note 1: The ADCDR2<EOCF> is cleared to "0" when reading the ADCDR1. Therfore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: The ADCDR2<ADBF> is set to "1" when AD conversion starts, and cleared to "0" when AD conversion finished. It also is cleared upon entering STOP mode or SLOW mode . Note 3: If a read instruction is executed for ADCDR2, read data of bit3 to bit0 are unstable. AD Converted value Register 1 ADCDR1 (0027H) 76543 210 AD09 AD08 AD07 AD06 AD05 AD04 AD03 AD02 (Initial value: 0000 0000) AD Converted value Register 2 ADCDR2 (0026H) 76543 210 AD01 AD00 EOCF ADBF (Initial value: 0000 ****) EOCF AD conversion end flag 0: 1: Before or during conversion Conversion completed Read only ADBF AD conversion BUSY flag 0: 1: During stop of AD conversion During AD conversion |
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