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TMP86FS23UG Datasheet(PDF) 57 Page - Toshiba Semiconductor |
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TMP86FS23UG Datasheet(HTML) 57 Page - Toshiba Semiconductor |
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57 / 252 page  Page 45 TMP86FS23UG 4. Special Function Register (SFR) The TMP86FS23UG adopts the memory mapped I/O system, and all peripheral control and data transfers are per- formed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86FS23UG. 4.1 SFR Address Read Write 0000H Reserved 0001H P1DR 0002H P2DR 0003H P3DR 0004H P3OUTCR 0005H P5DR 0006H P6DR 0007H P7DR 0008H P8DR 0009H P1CR 000AH P5CR 000BH P6CR1 000CH P6CR2 000DH P7CR 000EH ADCCR1 000FH ADCCR2 0010H TREG1AL 0011H TREG1AM 0012H TREG1AH 0013H TREG1B 0014H TC1CR1 TC1CR 0015H TC1CR2 0016H TC1SR - 0017H RTCCR 0018H TC3CR 0019H TC4CR 001AH TC5CR 001BH TC6CR 001CH TTREG3 001DH TTREG4 001EH TTREG5 001FH TTREG6 0020H ADCDR2 - 0021H ADCDR1 - 0022H Reserved 0023H Reserved 0024H P8CR 0025H UARTSR UARTCR1 |
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