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TMP86FS23UG Datasheet(PDF) 75 Page - Toshiba Semiconductor |
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TMP86FS23UG Datasheet(HTML) 75 Page - Toshiba Semiconductor |
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75 / 252 page ![]() Page 63 TMP86FS23UG Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. P7DR (0007H) R/W 76 543 21 0 P77 SEG8 P76 SEG9 P75 SEG10 P74 SEG11 P73 SEG12 P72 SEG13 P71 SEG14 P70 SEG15 (Initial value: 0000 0000) P7LCR (0FA0H) 76 543 21 0 (Initial value: 0000 0000) P7LCR Port P7/segment output control (set for each bit individually) 0: P7 input/output port 1: Segment output R/W P7CR (000DH) 76 543 21 0 (Initial value: 0000 0000) P7CR P7 port input/output control (set for each bit individually) 0: Input mode 1: Output mode R/W |
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