TMP86FS23UG datasheet(177/252 Pages) TOSHIBA

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Page 165

TMP86FS23UG

15.2.3 LCD drive voltage

LCD driving voltage VLCD is given as potential difference VDD

− VLC between pins VDD and VLC.

Therefore, when the CPU voltage and LCD drive voltage are the same, VLC pin will be connected to VSS pin.

The LCD lights when the potential difference between segment output and common output is ±VLCD. Other-

wise it turns off.

During reset, the power switch of LCD driver is automatically turned off, shutting off the VLC voltage.

After reset, if the P*LCR register (*; Port No.) for each port is set to “1” with LCDCR<EDSP> = “0”, a

GND level is output from the pin which can be used as segment.

The power switch is turned on to supply VLC voltage to LCD driver by setting with LCDCR<EDSP> to “1”.

If the IDLE0, SLEEP0, or STOP mode is activated, LCDCR<EDSP> is automatically changed to “0” to

blank the display. To turn the display back on after releasing from the previous mode, set LCDCR<EDSP> to

“1” again.

Note:During reset, the LCD common outputs (COM3 to COM0) are fixed “0” level. However, the multiplex port

(input/output port or SEG output is selectable) becomes high impedance. Therefore, when the reset input is

long remarkably, ghost problem may appear in LCD display.

15.2.4 Adjusting the LCD panel drive capability

The LCD panel drive capability can be adjusted by programming LCDCR<LRSE>. When the period of

enabling of the low bleeder resistor is lengthened, the drive capability becomes higher while the power con-

sumption increases. Reversely, when the period of enabling of the low bleeder resistor is shortened, the drive

capability becomes lower while the power consumption decreases. If the drive capability is not enough, the

LCD display might present a ghost problem. So, implement the optimum drive capability for the LCD panel

used. The figure below shows the bleeder resistance timing and equivalent circuit for 1/4 duty and 1/3 bias.

Figure 15-3 Bleeder Resistance Selection with LCDCR<LRSE> (for 1/4 duty and 1/3 bias)

VDD

VM1

VM2

VLCD

Frame frequency

RLt

When LCDCR

<LRSE>

"10B"

RLt RHt RLt RHt RLt RHt RLt RHt RLt RHt

When LCDCR

<LRSE> =

"00B" or "01B"

(a) ON Timing for Low Bleeder Resistance

VM2

VDD

VLC

High/low

resistance

switching

signal

RH: High resistance

RL: Low resistance

VLC

(b) Equivalent Circuit for

Bleeder Resistance

RLt: Period during which resistance RL is selected (Time specified with LCDCR<LRSE>)

RHt: Period during which resistance RH is selected

(Time specified with LCDCR<SLF>

÷ 4 − Time specified with LCDCR<LRSE>)

TMP86FS23UG Datasheet(PDF) 177 Page - Toshiba Semiconductor

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