PIC24FJ1024GA606 datasheet(55/470 Pages) MICROCHIP

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DS30010074G-page 55

PIC24FJ1024GA610/GB610 FAMILY

4.1.1

PROGRAM MEMORY

ORGANIZATION

The program memory space is organized in word-

addressable blocks. Although it is treated as 24 bits

wide, it is more appropriate to think of each address of

the program memory as a lower and upper word, with

the upper byte of the upper word being unimplemented.

The lower word always has an even address, while the

upper word has an odd address (Figure 4-3).

Program memory addresses are always word-aligned

on the lower word and addresses are incremented or

decremented by two during code execution. This

arrangement also provides compatibility with data

memory space addressing and makes it possible to

access data in the program memory space.

In Single Partition mode, user program memory is

arranged in a contiguous block starting at address,

000000h.

4.1.2

DUAL PARTITION FLASH PROGRAM

MEMORY ORGANIZATION

In the Dual Partition modes, the device’s memory is

divided evenly into two physical sections, known as

Partition 1 and Partition 2. Each of these partitions con-

tains its own program memory and Configuration

Words. During program execution, the code on only

one of these panels is executed; this is the Active

Partition. The other partition, or the Inactive Partition, is

not used, but can be programmed.

The Active Partition is always mapped to logical

address, 000000h, while the Inactive Partition will

always be mapped to logical address, 400000h. Note

that even when the code partitions are switched

between Active and Inactive by the user, the address of

the Active Partition will still be at 000000h and the

address of the Inactive Partition will still be at 400000h.

The Boot Sequence Configuration Word (FBTSEQ)

determines whether Partition 1 or Partition 2 will be active

after Reset. If the part is operating in Dual Partition mode,

the partition with the lower Boot Sequence Number will

operate as the Active Partition (FBTSEQ is unused in

Single Partition mode). The partitions can be switched

between Active and Inactive by reprogramming their

Boot Sequence Numbers, but the Active Partition will not

change until a device Reset is performed. If both Boot

Sequence Numbers are the same, or if both are

corrupted, the part will use Partition 1 as the Active Parti-

tion. If only one Boot Sequence Number is corrupted, the

device will use the partition without a corrupted Boot

Sequence Number as the Active Partition.

Should a Boot Sequence Number be invalid (or

unprogrammed), it will be overridden to value, 0x000FFF

(i.e., the highest possible Boot Sequence Number).

The user can also change which partition is active at run

time using the BOOTSWP instruction. Issuing a BOOTSWP

instruction does not affect which partition will be the

Active Partition after a Reset. Figure 4-2 demonstrates

how the relationship between Partitions 1 and 2, shown

in red and blue respectively, and the Active and Inactive

Partitions are affected by reprogramming the Boot

Sequence Number or issuing a BOOTSWP instruction.

The P2ACTIV bit (NVMCON[10]) can be used to deter-

mine which physical partition is the Active Partition. If

P2ACTIV = 1, Partition 2 is active; if P2ACTIV = 0,

Partition 1 is active.

4.1.3

HARD MEMORY VECTORS

All PIC24F devices reserve the addresses between

000000h and 000200h for hard-coded program execu-

tion vectors. A hardware Reset vector is provided to

redirect code execution from the default value of the PC

on a device Reset to the actual start of code. A GOTO

instruction is programmed by the user at 000000h, with

the actual address for the start of code at 000002h.

The PIC24FJ1024GA610/GB610 devices can have up to

two Interrupt Vector Tables (IVT). The first is located from

addresses, 000004h to 0000FFh. The Alternate Interrupt

Vector Table (AIVT) can be enabled by the AIVTDIS Con-

figuration bit if the Boot Segment (BS) is present. If the

user has configured a Boot Segment, the AIVT will be

located at the address, (BSLIM[12:0] – 1) x 0x800. These

vector tables allow each of the many device interrupt

sources to be handled by separate ISRs. A more detailed

discussion of the Interrupt Vector Tables is provided in

Section 8.1 “Interrupt Vector Table”.

4.1.4

CONFIGURATION BITS OVERVIEW

The Configuration bits are stored in the last page loca-

tion of implemented program memory. These bits can be

set or cleared to select various device configurations.

There are two types of Configuration bits: system oper-

ation bits and code-protect bits. The system operation

bits determine the power-on settings for system-level

components, such as the oscillator and the Watchdog

Timer. The code-protect bits prevent program memory

from being read and written.

Table 4-2 lists the Configuration register address range

for each device in Single and Dual Partition modes.

Table 4-2 lists all of the Configuration bits found in the

PIC24FJ1024GA610/GB610 family devices, as well as

their Configuration register locations. Refer to

Section 30.0 “Special Features” in this data sheet for

the full Configuration register description for each

specific device.

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