M58BW016DB datasheet(22/69 Pages) STMICROELECTRONICS

22 / 69 page

Bus operations

M58BW016DT, M58BW016DB, M58BW016FT, M58BW016FB

22/69

Valid Data Ready may be configured (by bit M8 of Burst Configuration Register) to be valid

immediately at the valid clock edge or one data cycle before the valid clock edge.

Synchronous Burst Read will be suspended if Burst Address Advance, B, goes High, VIH.

If Output Enable is at VIL and Output Disable is at VIH, the last data is still valid.

If Output Enable, G, is at VIH or Output Disable, GD, is at VIL, but the Burst Address

Advance, B, is at VIL the internal Burst Address counter is incremented at each Burst Clock

K valid edge.

The Synchronous Burst Read timing diagrams and AC characteristics are described in the

AC and DC parameters section. See Figure 13, Figure 14, Figure 15 and Figure 16, and

Table 20.

3.2.2

Synchronous Burst Read Suspend

During a Synchronous Burst Read operation it is possible to suspend the operation, freeing

the data bus for other higher priority devices.

A valid Synchronous Burst Read operation is suspended when both Output Enable and

Burst Address Advance are High, VIH. The Burst Address Advance going High, VIH, stops

the Burst counter and the Output Enable going High, VIH, inhibits the data outputs. The

Synchronous Burst Read operation can be resumed by setting Output Enable Low.

Table 6.

Synchronous Burst Read Bus operations(1)(2)

X = Don't care, VIL or VIH.

M15 = 0, bit M15 is in the Burst Configuration Register.

Bus operation

Step

K(3)

T = transition, see M6 in the Burst Configuration Register for details on the active edge of K.

A0-A18

DQ0-DQ31

Synchronous

Burst Read

Address Latch

VIL VIH

XVIH

TVIL

Address input

Read

VIL

VIL VIH VIH

TVIH VIL

Data output

Read Suspend

VIL VIH

XVIH

XVIH VIH

High-Z

Read Resume

VIL

VIL VIH VIH

TVIH VIL

Data output

Burst Address

Advance

VIL VIH

XVIH

TVIH VIL

High-Z

Read Abort, E

VIH

XXX

High-Z

Read Abort, RP

XXX

VIL

XXX

High-Z

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