6.3 Feature Description

6.3.1 DisplayPort

The TDP142-Q1 supports up to four DisplayPort lanes at data rates up to 8.1Gbps (HBR3). The TDP142-Q1

monitors the native AUX traffic as the device traverses between DisplayPort source and DisplayPort sink. For

the purposes of reducing power, the TDP142-Q1 manages the number of active DisplayPort lanes based on the

content of the AUX transactions. The TDP142-Q1 snoops native AUX writes to the DPCD registers 0x00101

(LANE_COUNT_SET) and 0x00600 (SET_POWER_STATE) of the DisplayPort sink. The TDP142-Q1 disables

or enables lanes based on the value written to LANE_COUNT_SET. The TDP142-Q1 disables all lanes when

SET_POWER_STATE is in the D3. Otherwise active lanes are based on value of LANE_COUNT_SET.

DisplayPort AUX snooping is enabled by default but can be disabled by changing the AUX_SNOOP_DISABLE

register. When AUX snoop is disabled, the TDP142-Q1 DisplayPort lanes are controlled through various

configuration registers. When TDP142-Q1 is enabled for GPIO mode (I2C_EN = "0"), the SNOOPENZ pin can

be used to disable AUX snooping. When SNOOPENZ pin is high, the AUX snooping functionality is disabled and

all four DisplayPort lanes are active.

6.3.2 Configuration Jumper Levels

The TDP142-Q1 EVM has 4-level inputs pins (I2C_EN, A0, and DPEQ[1:0]) that are used to control the

equalization gain and place the TDP142-Q1 into different modes of operation. These 4-level inputs use a resistor

divider to help set the four valid levels and provide a wider range of control settings. There are internal pullup

and pulldown resistors that can combine with the external resistor connection to achieve the desired voltage

level

Table 6-1. 4-Level Configuration Jumper Settings

LEVEL

SETTINGS

Low

Tie 1kΩ 5% to GND.

R

Tie 20kΩ 5% to GND.

F

Float (leave pin open)

High

Tie 1kΩ 5% to VCC.

.

Note

All 4-level inputs are latched on rising edge of internal reset. After tcfg_hd, the internal pullup and

pulldown resistors are isolated to save power.

6.3.3 Receiver Linear Equalization

The purpose of receiver equalization is to compensate for channel insertion loss and inter-symbol interference

in the system before the input of the TDP142-Q1. The receiver overcomes these losses by attenuating the

low-frequency components of the signals with respect to the high-frequency components. Select the proper gain

setting to match the channel insertion loss before the input of the TDP142-Q1 receivers. Two 4-level inputs pins

enable up to 16 possible equalization settings. The TDP142-Q1 also provides the flexibility of adjusting settings

through I2C registers.

www.ti.com

TDP142-Q1

SLLSG10A – NOVEMBER 2024 – REVISED FEBRUARY 2025

Copyright © 2025 Texas Instruments Incorporated

Submit Document Feedback

13

Product Folder Links: TDP142-Q1