STM32U385CG datasheet(45/224 Pages) STMICROELECTRONICS

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•

Independent clock: a choice of independent clock sources allowing the I2C communication speed to be

independent from the PCLK reprogramming

•

Autonomous functionality in Stop modes with wake-up from Stop capability

•

Programmable analog and digital noise filters

•

1-byte buffer with DMA capability

Table 13. I2C implementation

I2C features

I2C1

I2C2

I2C3

Standard-mode (up to 100 Kbit/s)

Fast-mode (up to 400 Kbit/s)

Fast-mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)

Programmable analog and digital noise filters

SMBus/PMBus hardware support

Independent clock

Autonomous in Stop 0, Stop 1 mode with wake-up capability

Autonomous in Stop 2 mode with wake-up capability

1. X = supported.

3.36

Improved inter-integrated circuit interface (I3C)

The devices embed two instances of I3C. The I3C interface handles communication between this device and

others, such as sensors and host processor, connected on an I3C bus. An I3C bus is a two-wire, serial single-

ended, multidrop bus, intended to improve a legacy I2C bus.

The I3C SDR-only peripheral implements all the features required by the MIPI® I3C specification v1.1. It can

control all I3C bus-specific sequencing, protocol, arbitration, and timing, and can act as controller (formerly known

as master), or as target (formerly known as slave).

When acting as controller, the I3C peripheral improves the features of the I²C interface preserving some backward

compatibility: it allows an I2C target to operate on an I3C bus in legacy I2C fast mode (Fm) or legacy I 2C fast

mode plus (Fm+), provided that the latter does not perform clock stretching.

The I3C peripheral can be used with DMA, to off-load the CPU.

The I3C peripheral supports:

•

MIPI® I3C specification v1.1, as:

–

I3C SDR-only primary controller

–

I3C SDR-only secondary controller

–

I3C SDR-only target

–

I3C SCL bus clock frequency up to 12.5 MHz

•

Registers configuration from the host application via the APB slave port

•

Queued data transfers:

–

Transmit FIFO (TX-FIFO) for data bytes/words to be transmitted on the I3C bus

–

Receive FIFO (RX-FIFO) for received data bytes/words on the I3C bus

–

For each FIFO, optional DMA mode with a dedicated DMA channel

•

Queued control/status transfers, when controller:

–

Control FIFO (C-FIFO) for control words to be sent on the I3C bus

–

Optional status FIFO (S-FIFO) for status words as received on the I3C bus

–

For each FIFO, optional DMA mode with a dedicated DMA channel

STM32U385xx

Functional overview

DS14830 - Rev 2

page 45/224

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