STM32U385CG datasheet(39/224 Pages) STMICROELECTRONICS

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Encrypt a shared key with a hardware secret key, with the result that stays hardware secret in write-only

SAES key registers (wrapped key mode)

•

Encrypt once a key using side-channel resistant AES, then share it to a faster AES engine by decrypting it

(shared key mode)

•

Decrypt a 256-bit random number using a 256-bit hardware secret master key, and use the result as a

device unique hardware secret key (to encrypt local data)

Note:

All hardware secret keys can no longer be used when a security breach is detected.

3.30

HASH hardware accelerator (HASH)

The hash processor is a fully compliant implementation of the secure hash algorithm (SHA1, SHA-2 family), and

the HMAC (keyed-hash message authentication code) algorithm. HMAC is suitable for applications requiring

message authentication.

The hash processor computes FIPS (Federal Information Processing Standards) approved digests of length of

160, 224, 256 bits, for messages of any length less than 264 bits (for SHA-1, SHA-224 and SHA-256) or less than

2128 bits (for SHA-384, SHA-512).

The HASH main features are:

•

Suitable for data authentication applications, compliant with:

–

Federal Information Processing Standards Publication FIPS PUB 180-4, Secure Hash Standard

(SHA-1 and SHA-2 family)

–

Federal Information Processing Standards Publication FIPS PUB 186-4, Digital Signature Standard

(DSS)

–

Internet Engineering Task Force (IETF) Request For Comments RFC 2104, HMAC: Keyed-Hashing

for Message Authentication and Federal Information Processing Standards Publication FIPS PUB

198-1, The Keyed-Hash Message Authentication Code (HMAC)

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Fast computation of SHA-1, SHA2-224, SHA2-256, SHA2-384, and SHA2-512

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82 (respectively 66) clock cycles for processing one 512-bit block of data using SHA-1 (respectively

SHA-256) algorithm

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Support for SHA-2 truncated outputs (SHA2-512/224, SHA2-512/256)

–

98 clock cycles for processing one 1024-bit block of data using either SHA2-384 or SHA2-512

algorithm

•

Corresponding 32-bit words of the digest from consecutive message blocks are added to each other to

form the digest of the whole message:

–

Automatic 32-bit words swapping to comply with the internal little-endian representation of the input

bit string

–

Supported word swapping format: bits, bytes, half-words, and 32-bit words

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Support for HMAC mode with all supported algorithm

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Automatic padding to complete the input bit string to fit digest minimum block size

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Single 32-bit, write-only, input register associated to an internal input FIFO, corresponding to a 64-byte

block size (16 x 32 bits)

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AHB slave peripheral, accessible by 32-bit words only (else an AHB error is generated)

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8 x 32-bit words (H0 to H7) for output messages

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Automatic data flow control with support of direct memory access (DMA) using one channel. Single or fixed

burst of 4 supported.

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Interruptible message digest computation, on a per-32-bit word basis

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Reloadable digest registers

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Hashing computation suspend/resume mechanism, including DMA

3.31

Public key accelerator (PKA)

The PKA is intended for the computation of cryptographic public key primitives, specifically those related to RSA,

Diffie-Hellmann, or ECC (elliptic curve cryptography) over GF(p) (Galois fields). To achieve high performance at a

reasonable cost, these operations are executed in the Montgomery domain.

For a given operation, all needed computations are performed within the accelerator, so no further hardware/

software elaboration is needed to process the inputs or the outputs.

STM32U385xx

Functional overview

DS14830 - Rev 2

page 39/224

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