ADXL356CEZ datasheet(39/52 Pages) AD

39 / 52 page

Data Sheet

ADXL356/ADXL357/ADXL357B

INTERRUPTS

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Rev. C | 39 of 52

EXT_SYNC = 00, EXT_CLK = 0—No External

Synchronization or Interpolation

This is the default mode of operation for the device. The sensor

runs on an internal ODR and an internal clock that is generated

by an internal oscillator. The internal ODR serves as the synchroni-

zation controller, which generates the data. Register 0x28 is used

to program the ODR. No external signals are required, and this

mode is used typically when the external processor retrieves data

from the device asynchronously and absolute synchronization to an

external source is not required.

The device outputs a DRDY (active high) to signal that a new sam-

ple is available, and data is retrieved from the real-time registers or

the FIFO. The group delay is based on the decimation setting, as

shown in Table 11. This mode is shown in Figure 101.

EXT_SYNC = 10, EXT_CLK = 0—External

Synchronization With Interpolation

Synchronization using interpolation filters and an external ODR

clock is commonly used when the external processor can provide a

synchronization signal, SYNC, that is asynchronous to the internal

clock at the desired ODR. In this case, an interpolation filter pro-

vides additional time resolution of 64 times the programmed ODR

(see Table 13). Synchronization with the interpolation filter enabled

(EXT_SYNC = 10) allows the sensor to operate on an internal clock

and output data most closely associated with the SYNC rising edge.

The advantage of this mode is that data is available at an arbitrary

user defined SYNC sample rate and is asynchronous to the internal

clock oscillator. The maximum sample rate cannot exceed 4000

SPS. The disadvantage of this mode is that the group delay is in-

creased, with increased attenuation at the band edge. Additionally,

because there is a limit to the time resolution, there is some distor-

tion related to the mismatch of the external synchronization relative

to the internal clock oscillator. This mismatch degrades spectral

performance. The group delay is based on the decimation setting

and interpolation setting (see Table 13). Figure 102 schematically

shows the timings in this mode, and Table 14 shows the delay

between the SYNC signal (input) to DRDY (output).

Table 14. EXT_SYNC = 10, DRDY Delay

ODR_LPF

SYNC to DRDY Delay (Oscillator Cycles)

0x0

0x1

0x2

0x3

0x4

0x5

0x6

134

0x7

262

Table 14. EXT_SYNC = 10, DRDY Delay (Continued)

ODR_LPF

SYNC to DRDY Delay (Oscillator Cycles)

0x8

1031

0x9

2054

0xA

4102

EXT_SYNC = 01, EXT_CLK = 1—External

Synchronization and External Clock, No

Interpolation Filter

When configured for EXT_SYNC = 01 and EXT_CLK = 1 (sync

(enabled via the EXT_CLK bit) at 1.024 MHz on the INT2 pin (Pin

13) and an external synchronization signal, SYNC, on the DRDY

pin (Pin 14), as shown in Table 15. If configured in this mode and

an external clock is not supplied, the device does not process any

data and reading from the output results in null values. This mode is

schematically shown in Figure 103.

Special restrictions when using this mode include the following:

►

The external clock frequency on INT2 (Pin 13, see Table 15)

must be 1.024 MHz.

►

The pulse width of the SYNC signal must be at least 3.91 µs,

which represents four cycles of the external clock (4 ÷ 1.024

MHz = ~3.91 µs).

►

The phase of SYNC must meet an approximate 25 ns setup time

to the external clock rising edge.

When using the EXT_SYNC mode and without providing the SYNC

signal, the device runs on its own internal ODR. Similarly, after

external synchronization, the device continues to run synchronized

to the last SYNC pulse it received, which means that EXT_SYNC =

01 mode can be used with only a single synchronization pulse.

For more information about the lost sample in Figure 103, see the

DRDY Pin section.

EXT_SYNC = 10, EXT_CLK = 1—External

Synchronization and External Clock, With

Interpolation Filter

This mode can be used to run the device on an external clock

and synchronization with an arbitrary sample rate set by the SYNC

signal rate. Conditions for external SYNC and external clock signals

is the same as EXT_SYNC = 01, EXT_CLK = 1 mode. The inter-

polation filter provides a frequency resolution related to the ODR

(see Table 13). In this case, the data provided corresponds to the

external SYNC signal, which can be greater than the set ODR and

less than 4000 SPS, but the output pass band remains the same it

was prior to the interpolation filter.

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