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TLV5618AMDREP Datasheet(PDF) 6 Page - Texas Instruments |
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TLV5618AMDREP Datasheet(HTML) 6 Page - Texas Instruments |
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6 / 18 page ![]() TLV5618AEP 2.7V TO 5.5V LOW POWER DUAL 12BIT DIGITALTOANALOG CONVERTER WITH POWER DOWN SGLS214 − OCTOBER 2003 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 digital input timing requirements MIN NOM MAX UNIT tsu(CS-CK) Setup time, CS low before first negative SCLK edge 10 ns tsu(C16-CS) Setup time, 16th negative SCLK edge before CS rising edge 10 ns tw(H) SCLK pulse width high 25 ns tw(L) SCLK pulse width low 25 ns tsu(D) Setup time, data ready before SCLK falling edge 8 ns th(D) Hold time, data held valid after SCLK falling edge 10 ns th(CSH) Hold time, CS high between cycles VDD = 5 V 25 ns th(CSH) Hold time, CS high between cycles VDD = 3 V 50 ns timing requirements tw(L) SCLK CS DIN D15 D14 D13 D12 D1 D0 X X 1 X 2 3 4 5 15 16 X tw(H) tsu(D) th(D) tsu(CS-CK) tsu(C16-CS) Figure 1. Timing Diagram |
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