DAC8501 datasheet(13/20 Pages) TI2

13 / 20 page

DAC8501

SBAS212A

www.ti.com

POWER-ON RESET

The DAC8501 contains a power-on reset circuit that controls

the output voltage during power-up. On power-up, the DAC

remains there until a valid write sequence is made to the

DAC. This is useful in applications where it is important to

know the state of the output of the DAC when it is in the

process of powering up.

POWER-DOWN MODES

The DAC8501 supports four separate modes of operation

which are programmable by setting two bits (PD1 and PD0)

in the control register. Table I shows how the state of the bits

corresponds to the mode of operation of the device.

MICROPROCESSOR

INTERFACING

DAC8501 TO 8051 INTERFACE

Figure 6 shows a serial interface between the DAC8501 and

a typical 8051-type microcontroller. The setup for the inter-

face is as follows: TXD of the 8051 drives SCLK of the

DAC8501, whereas RXD drives the serial data line of the

part. The SYNC signal is derived from a bit-programmable

pin on the port, in this case, port line P3.3 is used. When data

is to be transmitted to the DAC8501, P3.3 is taken LOW. The

8051 transmits data only in 8-bit bytes; thus only eight falling

clock edges occur in the transmit cycle. To load data to the

DAC, P3.3 is left LOW after the first eight bits are transmitted,

and a second write cycle is initiated to transmit the second

byte of data. P3.3 is taken HIGH following the completion of

the third write cycle. The 8051 outputs the serial data in a

format which has the LSB first. The DAC8501 requires its

data with the MSB as the first bit received, therefore the 8051

transmit routine must take this into account, and mirror the

data as needed.

PD1 (DB17)

PD0 (DB16)

OPERATING MODE

Normal Operation

——

Power-Down Modes

Output 1k

Ω to GND

Output 100k

Ω to GND

High-Z

TABLE I. Modes of Operation for the DAC8501.

DAC8501 TO Microwire INTERFACE

Figure 7 shows an interface between the DAC8501 and any

Microwire compatible device. Serial data is shifted out on the

falling edge of the serial clock and is clocked into the

DAC8501 on the rising edge of the SK signal.

FIGURE 5. Output Stage During Power-Down.

All linear circuitry is shut down when the power-down mode

is activated, however, the contents of the DAC register are

unaffected when in power-down. The time to exit power-

down is typically 2.5

µs for V

DD = 5V, and 5µs for VDD = 3V,

(see the Typical Characteristics for more information).

When both bits are set to 0, the part works normally with its

typical current consumption of 250

µA at 5V; however, for the

three power-down modes, the supply current falls to 200nA

at 5V (50nA at 3V). Not only does the supply current fall, but

the output stage is also internally switched from the output of

the amplifier to a resistor network of known values, this has

the advantage that the output impedance of the part is known

while the part is in power-down mode. There are three

different options: the output is connected internally to GND

through a 1k

Ω resistor; a 100kΩ resistor; or it is left open-

circuited (High-Z), Figure 5 shows the output stage.

FIGURE 6. DAC8501 to 80C51/80L51 Interface.

FIGURE 7. DAC8501 to Microwire Interface.

Resistor

String DAC

Amplifier

Power-Down

Circuitry

Resistor

Network

OUT

80C51/80L51(1)

P3.3

TXD

RXD

DAC8501(1)

SYNC

SCLK

NOTE: (1) Additional pins omitted for clarity.

SYNC

SCLK

MicrowireTM

DAC8501(1)

NOTE: (1) Additional pins omitted for clarity.

DAC8501 Datasheet(PDF) 13 Page - Texas Instruments

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