| Electronic Components Datasheet Search |
|
MPC8358E Datasheet(PDF) 17 Page - Freescale Semiconductor, Inc |
|
|
|||||||||||||||||||||||||||||
MPC8358E Datasheet(HTML) 17 Page - Freescale Semiconductor, Inc |
|
17 / 112 page ![]() MPC8360E/MPC8358E PowerQUICC™ II Pro Processor Revision 2.x TBGA Silicon Hardware Specifications, Rev. 2 Freescale Semiconductor 17 RESET Initialization 5.1 RESET DC Electrical Characteristics Table 9 provides the DC electrical characteristics for the RESET pins of the device. 5.2 RESET AC Electrical Characteristics This section describes the AC electrical specifications for the reset initialization timing requirements of the device. Table 10 provides the reset initialization AC timing specifications for the DDR SDRAM component(s). Table 9. RESET Pins DC Electrical Characteristics Characteristic Symbol Condition Min Max Unit Input high voltage VIH 2.0 OVDD + 0.3 V Input low voltage VIL –0.3 0.8 V Input current IIN ±10 μA Output high voltage VOH IOH = –8.0 mA 2.4 — V Output low voltage VOL IOL = 8.0 mA — 0.5 V Output low voltage VOL IOL = 3.2 mA — 0.4 V Notes: 1. This table applies for pins PORESET, HRESET, SRESET and QUIESCE. 2. HRESET and SRESET are open drain pins, thus VOH is not relevant for those pins. Table 10. RESET Initialization Timing Specifications Parameter/Condition Min Max Unit Notes Required assertion time of HRESET or SRESET (input) to activate reset flow 32 — tPCI_SYNC_IN 1 Required assertion time of PORESET with stable clock applied to CLKIN when the device is in PCI host mode 32 — tCLKIN 2 Required assertion time of PORESET with stable clock applied to PCI_SYNC_IN when the device is in PCI agent mode 32 — tPCI_SYNC_IN 1 HRESET/SRESET assertion (output) 512 — tPCI_SYNC_IN 1 HRESET negation to SRESET negation (output) 16 — tPCI_SYNC_IN 1 Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI host mode 4— tCLKIN 2 Input setup time for POR config signals (CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV) with respect to negation of PORESET when the device is in PCI agent mode 4— tPCI_SYNC_IN 1 Input hold time for POR config signals with respect to negation of HRESET 0— ns |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |